HFA3841
TM
PRELI MINARY
Data Sheet
January 2000
File Number
4661.2
Wireless LAN Medium Access Controller
The Intersil HFA3841 Wireless LAN
Medium Access Controller is part of the
PRISM® Enterprise 2.4GHz WLAN
chip set. The HFA3841 directly
interfaces with the Intersil HFA386x
family of Baseband Processors, offering a complete end-to-
end chip set solution for wireless LAN products. Protocol and
PHY support are implemented in firmware to allow custom
protocol and different PHY transceivers.
The HFA3841 is designed to provide maximum performance
with minimum power consumption. External pin layout is
organized to provide optimal PC board layout to all user
interfaces.
Firmware implements the full IEEE 802.11 Wireless LAN
MAC protocol. It supports BSS and IBSS operation under
DCF, and operation under the optional Point Coordination
Function (PCF). Low level protocol functions such as
RTS/CTS generation and acknowledgement, fragmentation
and de-fragmentation, and automatic beacon monitoring are
handed without host intervention. Active scanning is
performed autonomously once initiated by host command.
Host interface command and status handshakes allow
concurrent operations from multi-threaded I/O drivers.
Additional firmware functions specific to access point
applications are also available.
Designing wireless protocol systems using the HFA3841 is
made easier with the availability of evaluation board,
firmware, software device drivers, and complete
documentation.
Features
• IEEE802.11 Standard Data Rates: 1, 2, 5.5 and 11Mbps
• Part of the Intersil PRISM Wireless LAN Chip Set
• Full Implementation of the MAC Protocol Specified in
IEEE Std. 802.11-1999 and the 802.11b Draft Standard
• Host Interface Supports Full 16-Bit Implementation of PC
Card 95, also ISA PnP with Additional Chip
• Host Interface Provides Dual Buffer Access Paths
• External Memory Interface Supports up to 4M bytes RAM
• Internal Encryption Engine Executes IEEE802.11 WEP
• Low Power Operation; 25mA Active, 8mA Doze, <1mA Sleep
• Operation at 2.7V to 3.6V Supply
• 3V to 5V Tolerant Input/Outputs
• 128 Pin LQFP Package Targeted for Type II PC Cards
• IEEE802.11 Wireless LAN MAC Protocol Firmware and
Microsoft® Windows® Software Drivers
Applications
• High Data Rate Wireless LAN
• PC Card Wireless LAN Adapters
• ISA, ISA PnP WLAN Cards
• PCI Wireless LAN Cards (Using Ext. Bridge Chip)
• Wireless LAN Modules
• Wireless LAN Access Points
• Wireless Bridge Products
• Wireless Point-to-Multipoint Systems
Ordering Information
PART
NUMBER
HFA3841CN
HFA3841CN96
TEMP. RANGE
(
o
C)
0 to 70
0 to 70
PACKAGE
128 Ld LQFP
Tape and Reel
PKG. NO.
Q128.14x20
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
Microsoft® and Windows® are registered trademarks of Microsoft Corporation.
1-888-INTERSIL or 321-724-7143
|
Intersil and Design is a trademark of Intersil Corporation.
|
Copyright
©
Intersil Corporation 2000
PRISM® is a registered trademark of Intersil Corporation. PRISM logo is a trademark of Intersil Corporation.
Preliminary - HFA3841
Pinout
HREG-
HD0
HD1
HD2
V
CC
_IO3
V
SS
_IO3
HD8
HD9
HD10
PL7
MA18
MA17
MA16
MA15
MA14
MA13
MA12
MA11
MA10
V
CC
_IO3
V
SS
_IO3
MA9
MA8
MA7
MA6
MA5
MA4
MA3
MA2
NVCS-
V
SS
_IO3
V
CC
_IO3
MA1
MA0
MWEL-
MOE-
RAMCS-
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
PJ4
HCE1-
HD7
HD6
HD5
HD4
HD3
PJ6
PJ5
PJ7
TCLKIN
PL6
PL5
V
SS
_CORE3
V
CC
_CORE3
PL0
RESET
TXD
TXC
RXD
RXC
PK5
PK6
PK7
V
SS
_CORE3
V
CC
_CORE3
PL2
PL1
PL3
PJ3
PJ1
PJ0
PJ2
PK2
PK1
PK0
HSTSCHG-
V
SS
_CORE3
Simplified Block Diagram
PRISM RADIO
BASEBAND
PROCESSOR
TXD/RXD
CTRL/STATUS
SERIAL CONTROL
HFA3841
MICRO-
PROGRAMMED
MAC ENGINE
PC CARD
HOST
INTERFACE
HOST
COMPUTER
PHY
INTERFACE
(MDI)
WEP
ENGINE
DATA
ADDRESS
CONTROL
PRISM RADIO
RF SECTION
SERIAL
CONTROL
(MMI)
MEMORY
CONTROLLER
ON-CHIP
MEMORY
RADIO AND SYNTH
SERIAL CONTROL
ADDRESS
44MHz CLOCK
SOURCE
EXTERNAL
SRAM AND
FLASH
MEMORY
SELECT
DATA
2
CLKOUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
HINPACK-
HWAIT-
V
CC
_IO5
HA0
HA1
HA2
HA3
HA4
HA5
HA6
HA7
HIREQ-
V
SS
_IO3
HWE-
HA8
HA9
HIOWR-
HIORD-
HOE-
HCE2-
HD15
V
CC
_IO3
HD14
HD13
HD12
HD11
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
INDEX
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
PK4
PK3
TRST-
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
V
CC
_CORE3
V
SS
_IO3
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
PL4
V
SS
_IO3
XTALO
XTALI
V
CC
_CORE3
Preliminary - HFA3841
HFA3841 Pin Descriptions
Host Interface Pins
PIN NAME
HA0-9
HCE1-
HCE2-
HD0-15
PIN NUMBER
PIN I/O TYPE
DESCRIPTION
PC Card address input, bits 0 to 9
PC Card card select, low byte
PC Card card select, high byte
PC Card data bus, bit 0 to 15
106-113, 117, 118 5V tol, CMOS, Input, 50K Pull Down
1
122
101-99, 6-2,
96-94, 128-125,
123
103
120
119
114
5V tol, CMOS, Input, 50K Pull Up
5V tol, CMOS, Input, 50K Pull Up
5V tol, BiDir, 2mA, 50K Pull Down
HINPACK-
HIORD-
HIOWR-
HRDY/HIREQ-
CMOS Output, 2mA
5V tol, CMOS, Input, 50K Pull Up
5V tol, CMOS, Input, 50K Pull Up
CMOS Output, 4mA
PC Card I/O decode confirmation
PC Card I/O space read
PC Card I/O space write
PC Card interrupt request (I/O mode) Card ready
(memory mode)
PC Card memory attribute space output enable
PC Card attribute space select
HOE-
HREG-
HRESET
121
102
16
5V tol, CMOS, Input, 50K Pull Up
5V tol, CMOS, Input, 50K Pull Up
5V tol, CMOS, ST Input, 50K Pull Up Hardware Re-
set
CMOS Output, 4mA
CMOS Output, 4mA
5V tol, CMOS Input, 50K Pull Up
HSTSCHG-
HWAIT-
HWE-
36
104
116
PC Card status change
PC Card not ready (force host wait state)
PC Card memory attribute space write enable
Memory Interface Pins
PIN NAME
MA0 MWEH-
PIN NUMBER
72
PIN I/O TYPE
CMOS TS Output, 2mA
DESCRIPTION
MBUS address bit 0 (byte) for x8 memory High byte
write enable for x16 memory
MBUS address bits 1 to 18
MBUS address bit 19
MBUS address bit 20
MBUS address bit 21
Memory output enable
Low (or only) byte memory write enable
RAM select
NV memory select
MBUS low data byte, bits 0 to 7
MBUS high data byte, bits 8 to 15
MA1-18
PL4
PL5
PL6
MOE-
MWEL-
RAMCS-
NVCS-
MD0-7
MD8-15
73-81, 84-92
43
12
11
70
71
69
68
61-54
51-44
CMOS TS Output, 2mA
CMOS BiDir, 2mA
CMOS BiDir, 2mA, 50K Pull Up
CMOS BiDir, 2mA
CMOS TS Output, 2mA
CMOS TS Output, 2mA
CMOS TS Output, 2mA
CMOS TS Output, 2mA
5V tol, CMOS, BiDir, 2mA, 100K Pull Up
5V tol, CMOS, BiDir, 2mA 50K Pull Down
3
Preliminary - HFA3841
Radio Interface and General Purpose Port Pins
PIN NAME
TXD
TXC
RXD
RXC
PJ0
PJ1
PJ2
PJ3
PJ4
PJ5
PJ6
PJ7
PK0
PK1
PK2
PK3
PK4
PK5
PK6
PK7
PL0
PL1
PL2
PL3
PL4
PL5
PL6
PL7
PIN NUMBER
17
18
19
20
31
30
32
29
65
8
7
9
35
34
33
63
64
21
22
23
15
27
26
28
43
12
11
93
PIN I/O TYPE
CMOS Output, 2mA, 50K Pull Down
5V tol, CMOS, BiDir 2mA, ST
CMOS Input
CMOS Input, ST
CMOS BiDir, 2mA, ST, 50K Pull Down
CMOS BiDir, 2mA, 50K Pull Down
CMOS BiDir, 2mA, 50K Pull Down
CMOS BiDir, 2mA
CMOS BiDir, 2mA
CMOS BiDir, 2mA, 50K Pull Up
CMOS BiDir, 2mA
CMOS BiDir, 2mA, 50K Pull Up
CMOS BiDir, 2mA, ST, 50K Pull Down
CMOS BiDir, 2mA, 50K Pull Down
CMOS BiDir, 2mA, 50K Pull Down
CMOS BiDir, 2mA
CMOS BiDir, 2mA
CMOS BiDir, 2mA
CMOS BiDir, 2mA
CMOS BiDir, 2mA
CMOS BiDir, 2mA
CMOS BiDir, 2mA
CMOS BiDir, 2mA
CMOS BiDir, 2mA
CMOS BiDir, 2mA
CMOS BiDir, 2mA, 50K Pull Up MBUS address bit
20
CMOS BiDir, 2mA
CMOS BiDir, 2mA
MBUS address bit 21 or PHY control I/O
Transmitter ready
MBUS address bit 19
Transmitter enable
Receiver enable (or PHY sleep control)
MDREADY - PHY or MAC data available (in)
Medium busy (CCA from PHY)
DESCRIPTION OF FUNCTION
(IF OTHER THAN IO PORT)
Transmit data out
Transmit clock in/out
Receive data in
Receive clock in
MMI serial clock in/out
MMI serial data in/out
MMI serial data read/write control, or data output
MMI device enable
Clocks
PIN NAME
XTALI
XTALO
CLKOUT
TCLKIN
PIN NUMBER
40
41
38
10
CMOS Input, ST
CMOS Output, 2mA
CMOS, TS Output, 2mA
CMOS Input, ST, 50K Pull Down
PIN I/O TYPE
DESCRIPTION
Crystal or external clock input (at >= 2X desired
MCLK frequency)
Crystal output
Clock output (selectable as OSC or MCLK)
Timebase Reference Clock Input
4
Preliminary - HFA3841
Power
PIN NAME
VCC_CORE3
VCC_IO3
VCC_IO5
VSS_CORE3
VSS_IO3
TRST-
PIN NUMBER
14, 25, 39, 53
66, 83, 98. 124
105
13, 24, 37
42, 52, 67, 82, 97, 115
62
PIN I/O TYPE
3.3V Core Supply
3.3V I/O Supply
5V Tolerance Supply
Core V
SS
I/O V
SS
CMOS Input
Reserved - Must be tied low through 1K
DESCRIPTION
ST = Schmitt Trigger (Hysteresis), TS = Three-State. Signals ending with “-” are active low.
NOTE: Output pins typically drive to positive voltage rail less 0.1V. Hence with a supply of 2.7V the output will just meet 5V TTL signal levels at
rated loads.
Port Pin Uses for PRISM Application
PIN
20
19
18
17
31
30
32
NAME
RXC
RXD
TXC
TXD
PJ0
PJ1
PJ2
PRISM I USE
RXC - Receive clock
RXD - Receive data
TXC - Transmit clock
TXD - Transmit data
SCLK - Clock for the SD serial bus.
SD - Serial bi-directional data bus
R/W - An input to the HFA3860A used to change
the direction of the SD bus when reading or writing
data on the SD bus.
PRISM II™ USE
RXC - Receive clock
RXD - Receive data
TXC - Transmit clock
TXD - Transmit data
SCLK - Clock for the SD serial bus.
SD - Serial bi-directional data bus
Not Used
29
65
8
PJ3
PJ4
PJ5
CS - A Chip select for the device to activate the se- CS_BAR - Chip select for HFA3861 baseband
rial control port. (active low)
(active low)
Not Used
PE1 - Power Enable 1
SYNTH_LE - Latches a frame of 22 bits after it has LE_IF - Load enable for HFA3783 Quad IF
been shifted by the SCLK into the synthesizer reg-
isters.
LED - Activity indicator
Not Used
Not Used
Not Used
Not Used
TX_PE_RF - Power Enable
RX_PE_RF - Power Enable
LED - Activity indicator
RADIO_PE - RF power enable
LE_RF - Load enable for HFA3983 RF chip
SYNTHCLK - Serial clock to front end chips
SYNTHDATA - Serial data to front end chips
PA_PE - Transmit PA power enable
PE2 - Power Enable 2
7
9
35
34
33
63
64
21
22
23
15
27
26
28
43
12
11
93
PJ6
PJ7
PK0
PK1
PK2
PK3
PK4
PK5
PK6
PK7
PL0
PL1
PL2
PL3
PL4
PL5
PL6
PL7
MD_RDY - Header data and data packet are ready MDREADY - Header data and data packet are
to be transferred from Baseband on RXD
ready to be transferred from Baseband on RXD
CCA - Signal that the channel is clear to transmit.
RADIO_PE - Master power control for the RF
section
CCA - Signal that the channel is clear to transmit.
CAL_EN - Calibration mode enable
TX_PE and PA_PE - Transmit Enable to Baseband TX_PE - Transmit Enable to Baseband
RX_PE - Receive Enable to Baseband
RESET - Reset to Baseband
Not Used
MA19 (if required)
MA20 (if required)
MA21 (if required)
RX_PE - Receive Enable to Baseband
RESET_BB - Reset Baseband
T/R-SW_BAR - Transient/Receive Control (Inverted)
MA19 (if required)
MA20 (if required)
Reserved
TX_RDY - Baseband ready to receive data on TXD T/R_SW - Transmit/Receive Control
(not used by firmware)
5
