Agilent HFCT-5801 155 Mb/s Single
Mode Fiber Transceiver for ATM,
SONET OC-3/SDH STM-1
Part of the Agilent METRAK family
Data Sheet
Features
• 1300 nm Single mode transceiver
for links up to 15 Km
• Compliant with T1.646-1995
Broadband ISDN and
T1E1.2/98-011R1 SONET network
to customer installation interface
standards
• Compliant with T1.105.06 SONET
physical layer specifications
standard
• Multisourced 2 x 9 pin-out
package style derived from 1 x 9
pin-out industry standard package
style
• Unconditionally eyesafe laser
IEC 825/CDRH Class 1 compliant
• Integral duplex SC connector
receptacle compatible with
TIA/EIA and IEC standards
• Laser bias monitor, power monitor
and transmitter disable functions
compliant with SONET objectives
• Two temperature ranges:
0°C - +70°C
HFCT-580IB/D
-40°C - +85°C HFCT-5801A/C
• Single +3.3 V power supply
operation and compatible LVPECL
logic interfaces
• Wave solder and aqueous wash
process compatible
• Manufactured in an ISO 9002
certified facility
• Considerable EMI margin to FCC
Class B
Description
General
The HFCT-5801 transceiver is a
high performance, cost effective
module for serial optical data
communications applications
specified for a data rate of
155 Mb/s. It is designed to provide
a SONET/SDH compliant link for
intermediate reach links
operating at +3.3 V input voltage.
The multisourced 2 x 9 footprint
package style is a variation of the
standard 1 x 9 package with an
integral Duplex SC connector
receptacle. The extra row of 9
pins provides connections for
laser bias and optical power
monitoring as well as providing
transmitter disable function. A
block diagram is shown in
Figure 1.
Applications
• ATM 155 Mb/s links for LAN
backbone switches and routers
• ATM 155 Mb/s links for WAN
core, edge and access switches
and routers
• ATM 155 Mb/s links for add/drop
multiplexers and demultiplexers
• SONET OC-3/SDH STM-1 (S-1.1)
interconnections
ELECTRICAL SUBASSEMBLY
DATA
DATA
POST
AMPLIFIER IC
PRE-
AMPLIFIER
IC
OPTICAL
SUB-
ASSEMBLIES
LASER
DRIVER
IC
PIN PHOTODIODE
SIGNAL DETECT
DATA
DATA
DUPLEX SC
RECEPTACLE
Transceiver Specified for Wide
Temperature Range Operation
The HFCT-5801 is specified for
operation over normal commercial
temperature range of 0° to +70°C
(HFCT-5801B/D) or the extended
temperature range of -40° to
+85°C (HFCT-5801A/C).
Characterization of the parts has
been performed over the ambient
operating temperature range in
an airflow of 2 m/s.
Other Members of Agilent SC Duplex
155 Mb/s Product Family
• HFCT-5805, 1300 nm single
mode transceiver for links up
to 15 km. The part is based on
the 1 x 9 industry standard
package and has an integral
duplex SC connector
receptacle
Applications Information
Typical BER Performance of Receiver
versus Input Optical Power Level
The HFCT-5801 transceiver can
be operated at Bit-Error-Rate
conditions other than the
required BER = 1 x 10
-10
of the
ATM Forum 155.52 Mb/s Physical
Layer Standard. The typical
trade-off of BER versus Relative
Input Optical Power is shown in
Figure 3. The Relative Input
Optical Power in dB is
referenced to the actual
sensitivity of the device. For BER
conditions better than 1 x 10
-10
,
more input signal is needed (+dB).
LASER
TRANSMIT POWER LASER BIAS
DISABLE MONITOR MONITOR
TOP VIEW
Figure 1. Block Diagram
Transmitter Section
The transmitter section of the
HFCT-5801 consists of a 1300 nm
InGaAsP laser in an eyesafe
optical subassembly (OSA) which
mates to the fiber cable. The laser
OSA is driven by a custom IC
which converts differential input
LVPECL logic signals into an
analog laser drive current.
The laser bias monitor circuit is
shown in Figure 2a, the power
monitor circuit in Figure 2b.
V
CC
Receiver Section
The receiver utilizes an InGaAs
PIN photodiode mounted
together with a transimpedance
preamplifier IC in an OSA. This
OSA is connected to a circuit
providing post-amplification
quantization, and optical signal
detection.
Receiver Signal Detect
Signal Detect is a basic fiber
failure indicator. This is a
single-ended LVPECL output. As
the input optical power is
decreased, Signal Detect will
switch from high to low (deassert
point) somewhere between
sensitivity and the no light input
level. As the input optical power
is increased from very low levels,
Signal Detect will switch back
from low to high (assert point).
The assert level will be at least
0.5 dB higher than the deassert
level.
3 k
W
10 R
3 k
W
L
MON
(+)
PIN 6
L
MON
(-)
PIN 5
V
EE
Figure 2a. Laser Bias Monitor
V
CC
P
OWER
3 k
W
M
ONITOR
P
IN
9
(R
EF TO
V
EE
)
30 k
W
V
REF
1.28 V
V
EE
Figure 2b. Power Monitor Circuit
2
10
-2
10
-3
10
-4
10
-5
10
-6
10
-7
10
-8
10
-9
10
-10
10
-11
10
-12
10
-13
10
-14
10
-15
BIT ERROR RATIO
LINEAR EXTRAPOLATION OF
10
-4
THROUGH 10
-7
DATA
BASED ON
ACTUAL DATA
-5 -4 -3 -2 -1 0
1
2
3
suppress noise from influencing
the fiber-optic transceiver
performance, especially the
receiver circuit. Proper power
supply filtering of V
CC
for this
transceiver is accomplished by
using the recommended, separate
filter circuits shown in Figure 4
for the transmitter and receiver
sections. These filter circuits
suppress V
CC
noise over a broad
frequency range, this prevents
receiver sensitivity degradation
due to V
CC
noise. It is
recommended that surface-mount
components be used. Use
tantalum capacitors for the 10 µF
capacitors and monolithic,
ceramic bypass capacitors for the
0.1 µF capacitors. Also, it is
recommended that a surface-
mount coil inductor of 3.3 µH be
Figure 3. Relative Input Optical Power
- dBm. Avg.
Recommended Circuit Schematic
In order to ensure proper
functionality of the HFCT-5801 a
recommended circuit is provided
in Figure 4. When designing the
circuit interface, there are a few
fundamental guidelines to follow.
For example, in the Recommended
Circuit Schematic figure the
differential data lines should be
treated as 50 ohm Microstrip or
stripline transmission lines. This
will help to minimize the parasitic
inductance and capacitance
effects. Proper termination of the
differential data signals will
prevent reflections and ringing
which would compromise the
signal fidelity and generate
unwanted electrical noise. Locate
termination at the received signal
end of the transmission line. The
length of these lines should be
kept short and of equal length.
For the high speed signal lines,
differential signals should be
used, not single-ended signals,
and these differential signals
need to be loaded symmetrically
to prevent unbalanced currents
from flowing which will cause
distortion in the signal.
Maintain a solid, low inductance
ground plane for returning signal
currents to the power supply.
Multilayer plane printed circuit
board is best for distribution of
V
CC
, returning ground currents,
forming transmission lines and
shielding, Also, it is important to
3
Rx
Tx
NO INTERNAL
CONNECTION
TOP VIEW
NO INTERNAL
CONNECTION
Rx
V
EER
18
RD
17
RD
16
SD
15
Tx
Rx
V
CCR
V
CCT
14
13
TD
12
TD
11
Tx
V
EET
10
NC
1
NC
2
NC
3
NC
4
L
MON
L
MON
(-) (+) Tx
DIS
5
6
7
NC
8
P
MON
9
C1 C7
C2 C8
V
CC
L1 L2
R2
C4
R1
R3
C5
R4
V
CC
TERMINATE
AT PHY
DEVICE
INPUTS
R6
R5
R7
C6
R8
C3
LOCATE
FILTER
AT VCC
PINS
R9
R10
TERMINATE AT
FIBER-OPTIC
TRANSCEIVER
INPUTS
TD
TD
RD
RD
SD
V
CC
NOTES:
THE SPLIT-LOAD TERMINATIONS FOR LVPECL SIGNALS NEED TO BE LOCATED AT THE INPUT
OF DEVICES RECEIVING THOSE LVPECL SIGNALS. RECOMMEND 4-LAYER PRINTED CIRCUIT
BOARD WITH 50 W MICROSTRIP SIGNAL PATHS BE USED.
R1 = R4 = R6 = R8 = R10 = 82
W
R2 = R3 = R5 = R7 = R9 = 130
W
C1 = C2 = 10 µF
C3 = C4 = C7 = C8 = 100 nF
C5 = C6 = 0.1 µF.
L1 = L2 = 3.3 µH COIL OR FERRITE INDUCTOR.
Figure 4. Recommended Circuit Schematic
used. Ferrite beads can be used to
replace the coil inductors when
using quieter V
CC
supplies, but a
coil inductor is recommended
over a ferrite bead. All power
supply components need to be
placed physically next to the V
CC
pins of the receiver and
transmitter. Use a good, uniform
ground plane with a minimum
number of holes to provide a low-
inductance ground current return
for the power supply currents.
In addition to these
recommendations, Agilent’s
Application Engineering staff is
available for consulting on best
layout practices with various
vendors mux/demux, clock
generator and clock recovery
circuits. Agilent has participated
in several reference design
studies and is prepared to share
the findings of these studies with
interested customers. Contact
your local Agilent sales
representative to arrange for this
service.
Evaluation Circuit Boards
Evaluation circuit boards are
available from Agilent’s
Application Engineering staff.
Contact your local Agilent sales
representative to arrange for
access to one if needed.
Recommended Solder and Wash
Process
The HFCT-5801 is compatible
with industry standard wave or
hand solder processes.
A drying cycle must be
completed after wash process to
remove all moisture from the
module.
20.32
(0.8)
2 x Ø 1.9 ± 0.1
(0.075 ±0.004)
33.02
(1.3)
2.54
(0.1)
18 x Ø 0.8 ± 0.1
(0.032 ±0.004)
2.54
(0.1)
TOP VIEW
Figure 5. Recommended Board Layout Hole Pattern
HFCT-5801 Process Plug
The HFCT-5801 transceiver is
supplied with a process plug for
protection of the optical ports
with the Duplex SC connector
receptacle. This process plug
prevents contamination during
wave solder and aqueous rinse as
well as during handling, shipping
or storage. It is made of
high-temperature, molded,
sealing material that will
withstand +85°C and a rinse
pressure of 110 lb/in
2
.
Recommended Solder Fluxes
and Cleaning/Degreasing
Chemicals
Solder fluxes used with the
HFCT-5801 fiber-optic transceiver
should be water-soluble, organic
solder fluxes. Some recommended
solder fluxes are Lonco 3355-11
from London Chemical West, Inc.
of Burbank, CA, and 100 Flux
from Alpha- metals of Jersey
City, NJ.
Recommended cleaning and
degreasing chemicals for the
HFCT-5801 are alcohol’s (methyl,
isopropyl, isobutyl), aliphatics
(hexane, heptane) and other
chemicals, such as soap solution
or naphtha. Do not use partially
halogenated hydrocarbons for
cleaning/degreasing. Examples of
chemicals to avoid are 1.1.1.
trichloroethane, ketones (such as
MEK), acetone, chloroform, ethyl
acetate, methylene dichloride,
phenol, methylene chloride or
N-methylpyrolldone.
4
Agilent
ZZZZZ
TX
XXXX-XXXX
LASER PROD
21CFR(J) CLASS 1
COUNTRY OF ORIGIN YYWW
RX
KEY:
YYWW = DATE CODE
XXXX-XXXX = HFCT-5801
ZZZZ = 1300 nm
52.02
MAX.
(2.048)
12.7
(0.50)
25.4 MAX.
(1.00)
AREA
RESERVED
FOR
PROCESS
PLUG
12.7
(0.50)
11.1
10.35
MAX.
MAX.
(0.437)
(0.407)
0.75
(0.03)
+0.25
0.46 -0.05
18 x Ø
+0.010
0.018 -0.002
3.3
(0.130)
+0.25
1.27 -0.05
2xØ
+0.010
0.050 -0.002
20.32 8 x 2.54
(0.800)
(0.100)
20.32
(0.800)
2.54
(0.100)
33.02
(1.300)
15.88
(0.625
Note 1: SOLDER POSTS AND ELECTRICAL PINS ARE TIN/LEAD PLATED.
DIMENSIONS ARE IN MILLIMETERS (INCHES).
TOLERANCES: X.XX ±0.025mm
UNLESS OTHERWISE SPECIFIED.
X.X ±0.05 mm
1 = N/C
2 = N/C
3 = N/C
4 = N/C
5 = L
MON
(-)
6 = L
MON
(+)
7 = T
XDIS
8 = N/C
9 = P
MON
18 = V
EER
17 = RD
16 = RD-
15 = SD
14 = V
CCR
13 = V
CCT
12 = TD-
11 = TD+
10 = V
EET
TOP VIEW
N/C
RX
TX
N/C
Figure 6. Package Outline Drawing and Pinout
5
FPGA/CPLD
