HM52Y25165B-B6
HM52Y25405B-B6
EO
Description
Features
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256M SDRAM
100 MHz
4-Mword
×
16-bit
×
4-bank /16-Mword
×
4-bit
×
4-bank
E0146H10 (Ver. 1.0)
Preliminary
May. 28, 2001
The HM52Y25165B is a 256-Mbit SDRAM organized as 4194304-word
×
16-bit
×
4 bank. The
HM52Y25405B is a 256-Mbit SDRAM organized as 16777216-word
×
4-bit
×
4 bank. All inputs and outputs
are referred to the rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II.
2.5 V power supply
Clock frequency: 100MHz (max)
Single pulsed
RAS
4 banks can operate simultaneously and independently
Burst read/write operation and burst read/single write operation capability
Programmable burst length: 1/2/4/8
2 variations of burst sequence
Sequential (BL = 1/2/4/8)
Interleave (BL = 1/2/4/8)
Programmable
CAS
latency: 2, 3
Byte control by DQM : DQM (HM52Y25405B)
: DQMU/DQML (HM52Y25165B)
Refresh cycles: 8192 refresh cycles/64 ms
2 variations of refresh
Auto refresh
Self refresh
Preliminary: The Specifications of this device are subject to change without notice. Please contact to your
nearest Elpida Memory, Inc. regarding specifications.
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
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HM52Y25165B/ HM52Y25405B-B6
Ordering Information
Type No.
Frequency
100 MHz
100 MHz
CAS
latency
3
3
Package
400-mil 54-pin plastic TSOP II (TTP-54D)
EO
HM52Y25165BTT-B6*
1
HM52Y25405BTT-B6*
1
Note:
2
1. 66 MHz operation at
CAS
latency = 2.
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Preliminary Data Sheet E0146H10
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HM52Y25165B/ HM52Y25405B-B6
Pin Arrangement
(HM52Y25165B)
EO
Pin Description
Pin name
A0 to A12,
BA0, BA1
Function
Address input
Row address
DQ0 to DQ15
CS
RAS
CAS
Data-input/output
Chip select
54-pin TSOP
V
CC
DQ0
V
CC
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
CC
Q
DQ5
DQ6
V
SS
Q
DQ7
V
CC
DQML
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
CC
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
CC
Q
DQ8
V
SS
NC
DQMU
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
L
Column address
Bank select address BA0/BA1 (BS)
Row address strobe command
Column address strobe command
Pr
(Top view)
WE
A0 to A12
A0 to A8
CLK
CKE
V
CC
V
SS
V
CC
Q
V
SS
Q
NC
Preliminary Data Sheet E0146H10
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Pin name
Function
DQMU/DQML
Write enable
Input/output mask
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Clock input
Clock enable
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
t
3
HM52Y25165B/ HM52Y25405B-B6
Pin Arrangement
(HM52Y25405B)
EO
Pin Description
Pin name
A0 to A12,
BA0, BA1
Function
Address input
Row address
DQ0 to DQ3
CS
RAS
CAS
Data-input/output
Chip select
4
54-pin TSOP
V
CC
NC
V
CC
Q
NC
DQ0
V
SS
Q
NC
NC
V
CC
Q
NC
DQ1
V
SS
Q
NC
V
CC
NC
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
NC
V
SS
Q
NC
DQ3
V
CC
Q
NC
NC
V
SS
Q
NC
DQ2
V
CC
Q
NC
V
SS
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
L
Column address
Bank select address BA0/BA1 (BS)
Row address strobe command
Column address strobe command
Pr
(Top view)
WE
A0 to A12
A0 to A9, A11
DQM
CLK
CKE
V
CC
V
SS
V
CC
Q
V
SS
Q
NC
Preliminary Data Sheet E0146H10
od
Pin name
Function
Write enable
Input/output mask
Clock input
uc
Clock enable
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
t
HM52Y25165B/ HM52Y25405B-B6
Block Diagram
(HM52Y25165B)
Sense amplifier & I/O bus
Sense amplifier & I/O bus
Sense amplifier & I/O bus
Memory array
Memory array
Column decoder
Memory array
Column decoder
Sense amplifier & I/O bus
Column decoder
Column decoder
Preliminary Data Sheet E0146H10
5
DQMU
/DQML
CLK
CKE
RAS
CAS
WE
CS
EO
Column address
counter
Row decoder
Bank 0
8192 row
X 512 column
X 16 bit
A0 to A12, BA0, BA1
A0 to A12, BA0, BA1
A0 to A8
Column address
buffer
Row address
buffer
Refresh
counter
Row decoder
Row decoder
Row decoder
L
Memory array
Bank 1
Bank 2
Bank 3
8192 row
X 512 column
X 16 bit
8192 row
X 512 column
X 16 bit
8192 row
X 512 column
X 16 bit
Pr
Input
buffer
Output
buffer
DQ0 to DQ15
Control logic &
timing generator
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