240pin Registered DDR2 SDRAM DIMMs based on 1Gb version E
This Hynix Registered Dual In-Line Memory Module (DIMM) series consists of 1Gb version E DDR2
SDRAMs in Fine Ball Grid Array (FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1Gb
version E based Registered DDR2 DIMM series provide a high performance 8 byte interface in 5.25" width
form factor of industry standard. It is suitable for easy interchange and addition.
FEATURES
•
JEDEC standard Double Data Rate2 Synchro-
nous DRAMs (DDR2 SDRAMs) with 1.8V +/-
0.1V Power Supply
All inputs and outputs are compatible with
SSTL_1.8 interface
8 Bank architecture
Posted CAS
Programmable CAS Latency 3, 4, 5, 6
OCD (Off-Chip Driver Impedance Adjustment)
ODT (On-Die Termination)
•
•
•
•
•
•
•
•
Fully differential clock operations (CK & CK)
Programmable Burst Length 4 / 8 with both
sequential and interleave mode
Auto refresh and self refresh supported
8192 refresh cycles / 64ms
Serial presence detect with EEPROM
DDR2 SDRAM Package: 60 ball(x4/x8)
133.35 x 30.00 mm form factor
Halogen free & RoHS compliant
•
•
•
•
•
•
ORDERING INFORMATION
Part Name
HMP112P7EFR8C-C4/Y5/S6/S5
HMP125P7EFR4C-C4/Y5/S6/S5
HMP151P7EFR4C-C4/Y5/S6/S5
HMP31GP7EMR4C-C4/Y5
Density Organization
1GB
2GB
4GB
8GB
128Mx72
256Mx72
512Mx72
512Mx72
# of
DRAMs
9
18
36
72
# of
ranks
1
1
2
4
Materials
Halogen Free
Halogen Free
Halogen Free
Halogen Free
Parity
Support
O
O
O
O
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.2 / Sep. 2008
1
1
240pin Registered DDR2 SDRAM DIMMs
SPEED GRADE & KEY PARAMETERS
C4
(DDR2-533)
Speed@CL3
Speed@CL4
Speed@CL5
Speed@CL6
CL-tRCD-tRP
400
533
-
-
4-4-4
Y5
(DDR2-667)
400
533
667
-
5-5-5
S6
(DDR2-800)
-
533
667
800
6-6-6
S5
(DDR2-800)
400
533
800
-
5-5-5
Unit
Mbps
Mbps
Mbps
Mbps
tCK
ADDRESS TABLE
Density Organization
1GB
2GB
4GB
8GB
128M x 72
256M x 72
512M x 72
1G x 72
Ranks
1
1
2
4
SDRAMs
128Mb x 8
256Mb x 4
256Mb x 4
256Mb x 4
# of
DRAMs
9
18
36
72
# of row/bank/column Address
14(A0~A13)/3(BA0~BA2)/10(A0~A9)
14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11)
14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11)
14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11)
Refresh
Method
8K / 64ms
8K / 64ms
8K / 64ms
8K / 64ms
Rev. 0.2 / Sep. 2008
2
1
240pin Registered DDR2 SDRAM DIMMs
Input/Output Functional Description
Symbol
CK0
Type
IN
Polarity
Positive
Edge
Negative
Edge
Active High
Pin Description
Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
CK0
IN
Negative line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
CKE[1:0]
IN
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low. By deactivat-
ing the clocks, CKE low initiates the Power Down mode or the Self Refresh mode.
Enables the associated DDR2 SDRAM command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands are ignored but previous
operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1
On-Die Termination signals.
When sampled at the positive rising edge of the clock. RAS,CAS and WE(ALONG WITH S) define the
command being entered.
Reference voltage for SSTL18 inputs
Power supplies for the DDR2 SDRAM output buffers to provide improved noise immunity. For all current
DDR2 unbuffered DIMM designs, V
DDQ
shares the same power plane as V
DD
pins.
S[1:0]
IN
Active Low
ODT[1:0]
RAS, CAS, WE
Vref
V
DDQ
BA[2:0]
IN
IN
Supply
Supply
IN
Active High
Active Low
-
Selects which DDR2 SDRAM internal bank of Eight is activated.
During a Bank Activate command cycle, Address input difines the row address(RA0~RA13)
During a Read or Write command cycle, Address input defines the column address when sampled at the
cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used
to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high., autopre-
charge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is dis-
abled. During a Precharge command cycle., AP is used in conjunction with BA0-BAn to control which
bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn
inputs. If AP is low, then BA0-BAn are used to define which bank to precharge.
Data and Check Bit Input/Output pins.
A[9:0],A10/AP
A[13:11]
IN
-
DQ[63:0],
CB[7:0]
IN
-
DM[8:0]
IN
Active High
DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with
that input data during a write access. DM is sampled on both edges of DQS. Although DM pins are input
only, the DM loading matches the DQ and DQS loading.
Power and ground for the DDR2 SDRAM input buffers, and core logic. V
DD
and V
DDQ
pins are tied to
V
DD
/V
DDQ
planes on these modules.
V
DD
,V
SS
Supply
Positive
Edge
Negative
Edge
-
DQS[17:0]
I/O
Positive line of the differential data strobe for input and output data
DQS[17:0]
I/O
Negative line of the differential data strobe for input and output data
SA[2:0]
IN
These signals are tied at the system planar to either V
SS
or V
DDSPD
to configure the serial SPD
EEPROM address range.
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resister may be con-
nected from the SDA bus line to V
DDSPD
on the system planar to act as a pull up.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from
SCL to V
DDSPD
to act as a pull up on the system board.
Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power plane. EEPROM
supply is operable from 1.7V to 3.6V.
The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low, all
register outputs will be driven low and the PLL clocks to the DRAMs and register(s) will be set to low
level (the PLL will remain synchronized with the input clock)
Parity bit for the Address and Control bus(“1”. Odd, “0”.Even)
Parity error found in the Address and Control bus
Used by memory bus analysis tools (unused on memory DIMMs)
SDA
I/O
-
SCL
IN
-
VDDSPD
Supply
RESET
IN
Par_In
Err_Out
TEST
IN
OUT
Rev. 0.2 / Sep. 2008
3
1
240pin Registered DDR2 SDRAM DIMMs
PIN DESCRIPTION
Pin
CK0
CK0
CKE0~CKE1
RAS
CAS
WE
S0,S1
A0~A9,A11~A13
A10/AP
BA0, BA1, BA2
SCL
SDA
SA0~SA2
Par_In
Err_Out
RESET
CB0~CB7
Pin Description
Clock Input, positive line
Clock input, negative line
Clock Enable Input
Row Address Strobe
Column Address Strobe
Write Enable
Chip Select Input
Address input
Address input/Autoprecharge
SDRAM Bank Address
Serial Presence Detect (SPD) Clock Input
SPD Data Input/Output
E
2
PROM Address Inputs
Parity bit for the Address and Control bus
Parity error found on the Address
Reset Enable
Data Strobe Inputs/Outputs
Pin
ODT[1:0]
VDDQ
DQ0~DQ63
CB0~CB7
DQS(0~8)
DQS(0~8)
DM(0~8),DQS(9~17)
DQS(9~17)
RFU
NC
TEST
VDD
VDDQ
VSS
VREF
VDDSPD
Pin Description
On Die Termination Inputs
DQs Power Supply
Data Input/Output
Data check bits Input/Output
Data strobes
Data strobes, negative line
Data Maskes/Data strobes
Data strobes, negative line
Reserved for Future Use
No Connect
Memory bus test tool (Not Connected and Not
Usable on DIMMs)
Core Power
I/O Power Supply
Ground
Reference Power Supply
Power Supply for SPD
PIN LOCATION
pin #1
Front Side
Pin #64
Pin #65
Pin #120
Pin #121
Back Side
Pin #184
Pin #185
pin #240
Rev. 0.2 / Sep. 2008
4
1
240pin Registered DDR2 SDRAM DIMMs
PIN ASSIGNMENT
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Name
VREF
VSS
DQ0
DQ1
VSS
DQS0
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1
DQS1
VSS
RESET
NC
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DQS3
DQS3
VSS
DQ26
DQ27
Pin
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Name
VSS
CB0
CB1
VSS
DQS8
DQS8
VSS
CB2
CB3
VSS
VDDQ
CKE0
VDD
BA2,NC
NC, Err_Out
VDDQ
A11
A7
VDD
A5
A4
VDDQ
A2
VDD
Key
Pin
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
Name
DQ33
VSS
DQS4
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DQS5
DQS5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
SA2
NC(TEST)
VSS
DQS6
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DQS7
DQS7
VSS
DQ58
DQ59
VSS
SDA
SCL
Pin
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
Name
VSS
DQ4
DQ5
VSS
DM0/DQS9
DQS9
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1/DQS10
DQS10
VSS
RFU
RFU
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2/DQS11
DQS11
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DM3/DQS12
DQS12
VSS
DQ30
DQ31
VSS
Pin
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Name
CB4
CB5
VSS
DM8,DQS17
DQS17
VSS
CB6
CB7
VSS
VDDQ
NC,CKE1
VDD
A15,NC
A14,NC
VDDQ
A12
A9
VDD
A8
A6
VDDQ
A3
A1
VDD
Key
Pin
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
Name
VSS
DM4/DQS13
DQS13
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DM5/DQS14
DQS14
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
RFU
RFU
VSS
DM6/DQS15
NC,DQS15
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DM7/DQS16
NC,DQS16
VSS
DQ62
DQ63
VSS
VDDSPD
SA0
SA1
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
VSS
VSS
VDD
NC, Err_Out
VDD
A10/AP
BA0
VDDQ
WE
CAS
VDDQ
NC, S1
NC, ODT1
VDDQ
VSS
DQ32
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
CK0
CK0
VDD
A0
VDD
BA1
VDDQ
RAS
S0
VDDQ
ODT0
A13,NC
VDD
VSS
DQ36
DQ37
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
NC= No Connect, RFU= Reserved for Future Use.
Note:
1. RESET (Pin 18) is connected to both OE of PLL and Reset of register.
2. NC/Err_out (Pin 55) and NC/Par_In(Pin68) are for optional function to check address and command parity.
3. The Test pin (Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules (DIMMs)
Rev. 0.2 / Sep. 2008
5
DSP 与 ARM 处理器
