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HS-3374RH
August 2000
File Number
3038.2
Radiation Hardened 8-Bit Bidirectional
CMOS/TTL Level Converter
The Intersil HS-3374RH is a radiation hardened 8-bit
bidirectional level converter designed to interface CMOS
logic levels with TTL logic levels in radiation hardened bus
oriented systems. The HS-3374RH is fabricated using a
radiation hardened EPI-CMOS process and features eight
parallel bidirectional buffer/level converters.
Two control inputs, ENABLE and DISABLE, are used to
determine the direction of data flow, and to set both the in
puts and outputs in the high impedance state. The control
inputs may be driven by either TTL or CMOS logic drivers
capable of sinking one standard TTL load.
The HS-3374RH is a non-inverting version of the industry
standard CD40116. The non-inverting outputs of the
HS-3374RH reduce PC board chip count by eliminating the
need to restore data back to a non-inverted format.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-96786. A “hot-link” is provided
on our homepage for downloading.
www.intersil.com/spacedefense/space.asp
Features
• Electrically Screened to SMD # 5962-96786
• QML Qualified per MIL-PRF-38535 Requirements
• Radiation Hardened EPI-CMOS
- Total Dose . . . . . . . . . . . . . . . . . . . . . . 1 x 10
5
RAD(Si)
- Latch-Up Immune . . . . . . . >1 x 10
12
RAD(Si)/s (Note 1)
• Low Propagation Delay Time
- Typical CMOS to TTL Pre-RAD . . . . . . . . . . . . . . . 40ns
- Typical CMOS to TTL Post 100KRAD . . . . . . . . . . 40ns
- Typical TTL to CMOS Pre-RAD . . . . . . . . . . . . . . . 50ns
- Typical TTL to CMOS Post 100KRAD . . . . . . . . . . 50ns
• Low Standby Power
• +10V CMOS and +5V TTL Power Supply Inputs
• Eight Non-Inverting Three-State Input/Output Channels
• No External TTL Input Pull-Up Resistors Required
• High TTL Sink Current
• Equivalent to Sandia SA2996
• Military Temperature Range . . . . . . . . . . . . -55
o
C to 125
o
C
NOTE:
1. For operation at 10V and transient levels above
1 x 10
10
RAD(Si)/s, please refer to Application Note 401.
Ordering Information
ORDERING NUMBER
5962R9678601QWC
5962R9678601VWC
INTERNAL
MKT. NUMBER
HS1-3374RH-8
HS1-3374RH-Q
TEMP. RANGE
(
o
C)
-55 to 125
-55 to 125
Pinout
HS-3374RH
MIL-STD-1835, CDIP2-T22
(SBDIP)
TOP VIEW
VDD
A0
A1
VDD = 1
VCC = 22
GND = 11
A2
CMOS
INPUT/OUTPUT
A3
A4
A5
1
2
3
4
5
6
7
8
9
22 VCC
21 B0
20 B1
19 B2
18 B3
17 B4
16 B5
15 B6
14 B7
13 DISABLE
12 NC
TTL
INPUT/OUTPUT
Functional Diagram
DISABLE
13
CMOS
IN/OUT
8
2-9
LEVEL
SHIFTER
8
TTL
OUT (IN)
14-21
A6
A7
ENABLE 10
GND 11
ENABLE
10
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
HS-3374RH
Functional Block Diagram
1 OF 8 IDENTICAL CIRCUITS
VDD
VDD
VCC
2 (3, 4, 5, 6, 7, 8, 9)
A1 CMOS
INPUT (OUTPUT)
D
LEVEL
SHIFTER
E
GND
GND
GND
B1 TTL
OUTPUT
(INPUT)
21 (20, 19,
18, 17, 16,
15, 14)
VCC
DISABLE
13
VDD
LEVEL
SHIFTER
D
VDD
GND
ENABLE
10
LEVEL
SHIFTER
E
NOTES:
2. Enable and disable are TTL type inputs
3. D and E outputs are common to all 8 channels
INPUT (OUTPUT)
DATA
A0
A1
A2
A3
A4
A5
A6
A7
TERMINAL
NUMBER
2
3
4
5
6
7
8
9
OUTPUT (INPUT)
DATA
B0
B1
B2
B3
B4
B5
B6
B7
TERMINAL
NUMBER
21
20
19
18
17
16
15
14
ENABLE
X
1
0
DISABLE
0
1
1
TRUTH TABLE
FUNCTION
Convert CMOS Level to TTL Level
Convert TTL Level to CMOS Level
High Impedance (Z)
0 = Low Level 1 = High Level X = Don’t Care
Z = High Impedance on Both CMOS and TTL sides.
NOTE: An important caveat that is applicable to CMOS devices in
general is that unused inputs should never be left floating. This rule
applies to inputs connected to a three-state bus. The need for
external pull-up resistors during three-state bus conditions is
eliminated by the presence of regenerative latches on the following
HS-3374RH pins: A0 - 7.
The functional block diagram depicts one of these pins with the
regenerative latch. When the CMOS driver assumes the high
impedance state, the latch holds the bus in whatever logic state
(high or low) it was before the three-state condition. A transient
drive current of
±1.5mA
at VDD/2
±0.5V
for 10ns is required to
switch the latch. Thus, CMOS device inputs connected to the bus
are not allowed to float during three-state conditions.
WARNING: Do not activate the Disable input by hardwiring to any
TTL input pins. This is an incorrect mode of operation.
2
HS-3374RH
Die Characteristics
DIE DIMENSIONS:
89.4 mils x 76.0 mils x 14 mils
±1
mil
INTERFACE MATERIALS:
Glassivation:
Type: SiO2
Thickness: 11k
Å
±2k
Å
Top Metallization:
Type: AlSi
Thickness: 8k
Å
±1k
Å
Substrate:
Radiation Hardened Silicon Gate,
Dielectric Isolation
Backside Finish:
Silicon
ASSEMBLY RELATED INFORMATION:
Substrate Potential:
Unbiased (DI)
Metallization Mask Layout
HS-3374RH
(22) VCC
(1) VDD
(21) B0
(3) A1
(2) A0
(20) B1
A2 (4)
(19) B2
A3 (5)
(18) B3
A4 (6)
(17) B4
A5 (7)
(16) B5
A6 (8)
(15) B6
A7 (9)
(14) B7
ENABLE (10)
GND (11)
3
DISABLE (13)
