HS-1840ARH-T
Data Sheet
July 1999
File Number
4589.1
Radiation Hardened 16 Channel CMOS
Analog Multiplexer with High-Z Analog
Input Protection
Intersil’s Satellite Applications Flow
TM
(SAF) devices are fully
tested and guaranteed to 100kRAD Total Dose. These QML
Class T devices are processed to a standard flow intended
to meet the cost and shorter lead-time needs of large
volume satellite manufacturers, while maintaining a high
level of reliability.
The HS-1840ARH-T is a Radiation Hardened, monolithic 16
channel multiplexer constructed with the Intersil Rad-Hard
Silicon Gate, Dielectric Isolation process. It is designed to
provide a high input impedance to the analog source if
device power fails (open), or the analog signal voltage
inadvertently exceeds the supply by up to
±35V,
regardless
of whether the device is powered on or off. Selection of one
of sixteen channels is controlled by a 4-bit binary address
plus an Enable-Inhibit input, which conveniently controls the
ON/OFF operation of several multiplexers in a system. All
inputs have electrostatic discharge protection.
Features
• QML Class T, Per MIL-PRF-38535
• Radiation Performance
- Gamma Dose (γ) 1 x 10
5
RAD(Si)
- No Latch-Up, Dielectrically Isolated Device Islands
• Improved r
DS(ON)
Linearity
• Improved Access Time 1.5µs (Max) Over Temp and Rad
• High Analog Input Impedance 500MΩ During Power Loss
(Open)
•
±35V
Input Over Voltage Protection (Power On or Off)
• Excellent in Hi-Rel Redundant Systems
• Break-Before-Make Switching
Pinouts
HS1-1840ARH-T (SBDIP), CDIP2-T28
TOP VIEW
+V
S
1
NC 2
NC 3
IN 16 4
IN 15 5
IN 14 6
IN 13 7
IN 12 8
IN 11 9
IN 10 10
IN 9 11
GND 12
(+5V
S
) V
REF
13
ADDR A3 14
28 OUT
27 -V
S
26 IN 8
25 IN 7
24 IN 6
23 IN 5
22 IN 4
21 IN 3
20 IN 2
19 IN 1
18 ENABLE
17 ADDR A0
16 ADDR A1
15 ADDR A2
Specifications
Specifications for Rad Hard QML devices are controlled by
the Defense Supply Center in Columbus (DSCC). The SMD
numbers listed below must be used when ordering.
Detailed Electrical Specifications for the HS-1840ARH-T
are contained in SMD 5962-95630.
A “hot-link” is provided
from our website for downloading.
www.intersil.com/spacedefense/newsafclasst.asp
Intersil’s Quality Management Plan (QM Plan), listing all
Class T screening operations, is also available on our
website.
www.intersil.com/quality/manuals.asp
Ordering Information
ORDERING
NUMBER
5962R9563002TXC
HS1-1840ARH/Proto
5962R9563002TYC
HS9-1840ARH/Proto
PART
NUMBER
HS1-1840ARH-T
HS1-1840ARH/Proto
HS9-1840ARH-T
HS9-1840ARH/Proto
TEMP.
RANGE
(
o
C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
HS9-1840ARH-T (FLATPACK) CDFP3-F28
TOP VIEW
+V
S
NC
NC
IN 16
IN 15
IN 14
IN 13
IN 12
IN 11
IN 10
IN 9
GND
(+5V
S
) V
REF
ADDR A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OUT
-V
S
IN 8
IN 7
IN 6
IN 5
IN 4
IN 3
IN 2
IN 1
ENABLE
ADDR A0
ADDR A1
ADDR A2
NOTE:
Minimum order quantity for -T is 150 units through
distribution, or 450 units direct.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
www.intersil.com or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
Satellite Applications Flow™ (SAF) is a trademark of Intersil Corporation.
HS-1840ARH-T
Functional Diagram
A0
1
P
IN 1
A1
DIGITAL
ADDRESS
A2
OUT
A3
16
EN
P
IN 16
ADDRESS INPUT
BUFFER AND
LEVEL SHIFTER
DECODERS
MULTIPLEX
SWITCHES
TRUTH TABLE
A3
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
A2
X
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
A1
X
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
A0
X
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
EN
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
“ON” CHANNEL
None
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
2
HS-1840ARH-T
Die Characteristics
DIE DIMENSIONS:
(2820µm x 4080µm x 483µm
±25.4µm)
111 x 161 x 19mils
±1mil
METALLIZATION:
Type: Al Si Cu
Thickness: 16.0k
Å
±2k
Å
SUBSTRATE POTENTIAL:
Unbiased (DI)
BACKSIDE FINISH:
Silicon
PASSIVATION:
Type: Nitride (Si
3
N
4
) over Silox (S
i
O
2
)
Nitride Thickness: 4.0k
Å
±0.5k
Å
Silox Thickness: 12.0k
Å
±1.3k
Å
WORST CASE CURRENT DENSITY:
< 2.0e5 A/cm
2
TRANSISTOR COUNT:
407
PROCESS:
Radiation Hardened Silicon Gate, Dielectric Isolation
Metallization Mask Layout
HS-1840ARH-T
IN7
IN6
IN5
IN4
IN3
IN2
IN1
IN8
ENABLE
A0
-V
A1
OUT
A2
+V
A3
V
REF
IN16
GND
IN15
IN14
IN13
IN12
IN11
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
http://www.intersil.com
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