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DATASHEET

HS-26CLV32RH, HS-26CLV32EH

Radiation Hardened 3.3V Quad Differential Line Receivers

The Intersil

HS-26CLV32RH, HS-26CLV32EH

are radiation

hardened 3.3V quad differential line receivers designed for

digital data transmission over balanced lines, in low voltage,

RS-422 protocol applications. Radiation hardened CMOS

processing assures low power consumption, high speed, and

reliable operation in the most severe radiation environments.

The HS-26CLV32RH, HS-26CLV32EH have an input sensitivity

of 200mV (typical) over a common-mode input voltage range

of -4V to +7V. The receivers are also equipped with input

fail-safe circuitry, which causes the outputs to go to a logic “1”

when the inputs are open. The device has unique inputs that

remain high impedance when the receiver is disabled or

powered-down, maintaining signal integrity in multi-receiver

applications.

Specifications for Rad Hard QML devices are controlled by the

Defense Logistics Agency Land and Maritime (DLA). The SMD

numbers listed must be used when ordering.

FN4907

Rev 6.00

February 6, 2017

Features

• Electrically screened to SMD #

5962-95689

• QML qualified per MIL-PRF-38535 requirements

• 1.2 micron radiation hardened CMOS

- Total dose . . . . . . . . . . . . . . . . . . . . . . . . . 300krad(Si) (max)

- Single event upset LET . . . . . . . . . . . . . 100MeV/mg/cm

)

- Single event latch-up immune

• Low stand-by current . . . . . . . . . . . . . . . . . . . . . . . 13mA (max)

• Operating supply range . . . . . . . . . . . . . . . . . . . . . 3.0V to 3.6V

• Enable input levels. . . . . . . . .V

> 0.7 x V

; V

< 0.3 x V

• CMOS output levels . . . . . . . . . . . . . .V

> 2.55V; V

< 0.4V

• Input fail-safe circuitry

• High impedance inputs when disabled or powered-down

• Full -55°C to +125°C military temperature range

• Pb-free (RoHS compliant)

Related Literature

• For a full list of related documents, visit our website

HS-26CLV32RH

and

HS-26CLV32EH

product pages

Applications

• Line receiver for MIL-STD-1553 serial data bus

ENABLE

ENABLE DIN DIN

CIN CIN

BIN BIN

AIN AIN

DOUT

COUT

BOUT

AOUT

FIGURE 1. LOGIC DIAGRAM

FN4907 Rev 6.00

February 6, 2017

Page 1 of 6

HS-26CLV32RH, HS-26CLV32EH

Ordering Information

ORDERING SMD NUMBER

(Note

5962F9568902QEC

5962F9568902QXC

5962F9568902VEC

5962F9568902VXC

5962F9568902V9A

N/A

5962F9568904VEC

5962F9568904VXC

5962F9568904V9A

5962F9568904VYC

5962F9568902VYC

N/A

NOTES:

1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both

SnPb and Pb-free soldering operations.

2. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed must be

used when ordering.

3. The lid of these packages are connected to the ground pin of the device.

PART NUMBER (Note

HS1-26CLV32RH-8

HS9-26CLV32RH-8

HS1-26CLV32RH-Q

HS9-26CLV32RH-Q

HS0-26CLV32RH-Q

HS0-26CLV32RH/SAMPLE

HS1-26CLV32RH/PROTO

HS9-26CLV32RH/PROTO

HS1-26CLV32EH-Q

HS9-26CLV32EH-Q

HS0-26CLV32EH-Q

HS9G-26CLV32EH-Q (Note

HS9G-26CLV32RH-Q (Note

HS9G-26CLV32RH/PROTO (Notes

TEMP. RANGE

(°C)

-55 to +125

PACKAGE

(RoHS COMPLIANT)

16 Ld SBDIP

16 Ld Flatpack

16 Ld SBDIP

16 Ld Flatpack

Die

16 Ld SBDIP

16 Ld Flatpack

16 Ld SBDIP

16 Ld Flatpack

Die

16 Ld Flatpack

K16.A

D16.3

K16.A

D16.3

K16.A

PKG.

DWG. #

D16.3

K16.A

D16.3

K16.A

Pin Configurations

HS1-26CLV32RH, HS1-26CLV32EH

(16 LD SBDIP)

MIL-STD-1835: CDIP2-T16

TOP VIEW

AIN 1

AIN 2

AOUT 3

ENABLE 4

COUT 5

CIN 6

CIN 7

GND 8

16 V

15 BIN

14 BIN

13 BOUT

12 ENABLE

11 DOUT

10 DIN

9 DIN

AIN

AOUT

ENABLE

COUT

CIN

GND

HS9-26CLV32RH, HS9-26CLV32EH

(16 LD FLATPACK)

MIL-STD-1835: CDFP4-F16

TOP VIEW

BIN

BOUT

ENABLE

DOUT

DIN

NOTES:

4. For details on input output structures refer to application note

AN9520.

5. For details on package dimensions refer MIL STD 1835.

FN4907 Rev 6.00

February 6, 2017

Page 2 of 6

HS-26CLV32RH, HS-26CLV32EH

Die Characteristics

DIE DIMENSIONS:

78 mils x 123 mils x 21 mils

(1970µm x 3120µm)

Metallization:

Bottom: Mo/TiW

Thickness: 5800Å ±1kÅ

Top: Al/Si/Cu

Thickness: 10kÅ ±1kÅ

Worst Case Current Density:

<2.0 x 10

A/cm

Bond Pad Size:

110µmx100µm

INTERFACE MATERIALS:

Glassivation:

Type: PSG (Phosphorus Silicon Glass)

Thickness: 8kÅ ±1kÅ

Substrate:

AVLSI1RA, Silicon backside, V

backside potential

Metallization Mask Layout

HS-26CLV32RH, HS-26CLV32EH

AIN

(1)

(16)

BIN

(15)

TABLE 1. HS-26CLV32RH, HS-26CLV32EH PAD COORDINATES

NUMBER

PAD

NAME

AIN

AOUT

ENABLE

COUT

CIN

GND

DIN

DOUT

ENABLE

BOUT

BIN

RELATIVE TO PIN 1

X COORDINATES Y COORDINATES

-337.1

418.4

776.4

1113.5

776.4

420.2

-362

-912.5

-1319.3

-1774.4

-2233.7

-2595.7

-2596.7

-2595.7

-2233.7

-1774.4

-1319.3

-898.4

-362

AIN (2)

(14) BIN

AOUT (3)

(13) BOUT

ENAB (4)

(12) ENAB

COUT (5)

(11) DOUT

CIN (6)

(10) DIN

NOTE: Dimensions in microns

(7)

CIN

(8)

GND

(9)

DIN

FN4907 Rev 6.00

February 6, 2017

Page 3 of 6

HS-26CLV32RH, HS-26CLV32EH

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.

Please visit our website to make sure you have the latest revision.

DATE

February 6, 2017

REVISION

FN4907.6

CHANGE

Added Related Literature section.

Updated Ordering Information table on page 2.

Added Note 2 on page 2.

Added Revision History and About Intersil sections.

Added POD drawings.

Revision History

About Intersil

Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products

address some of the largest markets within the industrial and infrastructure, mobile computing, and high-end consumer markets.

For the most updated datasheet, application notes, related documentation, and related parts, see the respective product information

page found at

www.intersil.com.

For a listing of definitions and abbreviations of common terms used in our documents, visit:

www.intersil.com/glossary.

You may report errors or suggestions for improving this datasheet by visiting

www.intersil.com/ask.

Reliability reports are also available from our website at

www.intersil.com/support.

All trademarks and registered trademarks are the property of their respective owners.

For additional products, see

www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted

in the quality certifications found at

www.intersil.com/en/support/qualandreliability.html

Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such

modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are

current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its

subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see

www.intersil.com

FN4907 Rev 6.00

February 6, 2017

Page 4 of 6

HS-26CLV32RH, HS-26CLV32EH

Package Outline Drawing

K16.A

16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE

Rev 2, 1/10

0.015 (0.38)

0.008 (0.20)

PIN NO. 1

ID OPTIONAL

For the most recent package outline drawing, see

K16.4.

0.050 (1.27 BSC)

PIN NO. 1

ID AREA

0.440 (11.18)

MAX

0.005 (0.13)

MIN

0.022 (0.56)

0.015 (0.38)

TOP VIEW

0.115 (2.92)

0.045 (1.14)

0.026 (0.66)

0.285 (7.24)

0.245 (6.22)

0.009 (0.23)

0.004 (0.10)

-D-

-H-

-C-

0.13 (3.30)

MIN

0.370 (9.40)

0.250 (6.35)

SEATING AND

BASE PLANE

0.03 (0.76) MIN

LEAD FINISH

SIDE VIEW

NOTES:

1. Index area: A notch or a pin one identification mark shall be located

adjacent to pin one and shall be located within the shaded area shown.

The manufacturer’s identification shall not be used as a pin one

identification mark. Alternately, a tab may be used to identify pin one.

2. If a pin one identification mark is used in addition to a tab, the limits

of the tab dimension do not apply.

3. The maximum limits of lead dimensions (section A-A) shall be

measured at the centroid of the finished lead surfaces, when solder

dip or tin plate lead finish is applied.

4. Measure dimension at all four corners.

5. For bottom-brazed lead packages, no organic or polymeric materials

shall be molded to the bottom of the package to cover the leads.

SECTION A-A

6. Dimension shall be measured at the point of exit (beyond the

meniscus) of the lead from the body. Dimension minimum shall

be reduced by 0.0015 inch (0.038mm) maximum when solder dip

lead finish is applied.

7. Dimensioning and tolerancing per ANSI Y14.5M - 1982.

8. Controlling dimension: INCH.

0.006 (0.15)

0.004 (0.10)

LEAD FINISH

BASE

METAL

0.019 (0.48)

0.015 (0.38)

0.0015 (0.04)

MAX

0.009 (0.23)

0.004 (0.10)

0.022 (0.56)

0.015 (0.38)

FN4907 Rev 6.00

February 6, 2017

Page 5 of 6

参数对比

与HS9-26CLV32RH/PROTO相近的元器件有：HS1-26CLV32RH/PROTO、HS1-26CLV32EH-Q、HS1-26CLV32RH-8、HS0-26CLV32RH-Q、HS9-26CLV32RH-Q、HS1-26CLV32RH-Q。描述及对比如下：

型号	HS9-26CLV32RH/PROTO	HS1-26CLV32RH/PROTO	HS1-26CLV32EH-Q	HS1-26CLV32RH-8	HS0-26CLV32RH-Q	HS9-26CLV32RH-Q	HS1-26CLV32RH-Q
描述	QUAD LINE RECEIVER, CDFP16, CERAMIC, DFP-16	QUAD LINE RECEIVER, CDIP16, SIDE BRAZED, CERAMIC, DIP-16	IC,LINE RECEIVER,QUAD,CMOS, RAD HARD,DIFFERENTIAL,DIP,16PIN,CERAMIC	QUAD LINE RECEIVER, CDIP16, SIDE BRAZED, CERAMIC, DIP-16	QUAD LINE RECEIVER, UUC16, DIE-16	QUAD LINE RECEIVER, CDFP16, CERAMIC, DFP-16	QUAD LINE RECEIVER, CDIP16, SIDE BRAZED, CERAMIC, DIP-16
是否Rohs认证	符合	不符合	符合	符合	符合	符合	符合
包装说明	DFP,	DIP,	DIP, DIP16,.3	DIP, DIP16,.3	DIE,	DFP, FL16,.3	DIP, DIP16,.3
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant	compliant
输入特性	DIFFERENTIAL SCHMITT TRIGGER	DIFFERENTIAL SCHMITT TRIGGER	DIFFERENTIAL SCHMITT TRIGGER	DIFFERENTIAL SCHMITT TRIGGER	DIFFERENTIAL SCHMITT TRIGGER	DIFFERENTIAL SCHMITT TRIGGER	DIFFERENTIAL SCHMITT TRIGGER
接口集成电路类型	LINE RECEIVER	LINE RECEIVER	LINE RECEIVER	LINE RECEIVER	LINE RECEIVER	LINE RECEIVER	LINE RECEIVER
接口标准	EIA-422	EIA-422	EIA-422	EIA-422	EIA-422	EIA-422	EIA-422
JESD-30 代码	R-CDFP-F16	R-CDIP-T16	R-CDIP-T16	R-CDIP-T16	R-XUUC-N16	R-CDFP-F16	R-CDIP-T16
功能数量	4	4	4	4	4	4	4
端子数量	16	16	16	16	16	16	16
封装主体材料	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	UNSPECIFIED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
封装代码	DFP	DIP	DIP	DIP	DIE	DFP	DIP
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	FLATPACK	IN-LINE	IN-LINE	IN-LINE	UNCASED CHIP	FLATPACK	IN-LINE
峰值回流温度（摄氏度）	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
接收器位数	4	4	4	4	4	4	4
最大供电电压	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
最小供电电压	3 V	3 V	3 V	3 V	3 V	3 V	3 V
标称供电电压	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
表面贴装	YES	NO	NO	NO	YES	YES	NO
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
端子形式	FLAT	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	NO LEAD	FLAT	THROUGH-HOLE
端子位置	DUAL	DUAL	DUAL	DUAL	UPPER	DUAL	DUAL
处于峰值回流温度下的最长时间	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
总剂量	300k Rad(Si) V	300k Rad(Si) V	300k Rad(Si) V	300k Rad(Si) V	300k Rad(Si) V	300k Rad(Si) V	300k Rad(Si) V
是否无铅	含铅	含铅	-	不含铅	不含铅	不含铅	不含铅
零件包装代码	DFP	DIP	-	DIP	DIE	DFP	DIP
针数	16	16	-	16	16	16	16
ECCN代码	USML XV(E)	EAR99	-	EAR99	EAR99	USML XV(E)	EAR99
JESD-609代码	e4	e0	-	e4	e4	e4	e4
最高工作温度	125 °C	125 °C	125 °C	125 °C	-	125 °C	125 °C
最低工作温度	-55 °C	-55 °C	-55 °C	-55 °C	-	-55 °C	-55 °C
座面最大高度	2.92 mm	5.08 mm	5.08 mm	5.08 mm	-	2.92 mm	5.08 mm
温度等级	MILITARY	MILITARY	MILITARY	MILITARY	-	MILITARY	MILITARY
端子面层	Gold (Au)	TIN LEAD	-	Gold (Au)	Gold (Au)	Gold (Au)	Gold (Au)
端子节距	1.27 mm	2.54 mm	2.54 mm	2.54 mm	-	1.27 mm	2.54 mm
宽度	6.73 mm	7.62 mm	7.62 mm	7.62 mm	-	6.73 mm	7.62 mm
厂商名称	-	-	Renesas(瑞萨电子)	Renesas(瑞萨电子)	Renesas(瑞萨电子)	Renesas(瑞萨电子)	Renesas(瑞萨电子)
最大输出低电流	-	-	0.006 A	0.006 A	-	0.006 A	0.006 A
封装等效代码	-	-	DIP16,.3	DIP16,.3	-	FL16,.3	DIP16,.3
电源	-	-	3.3 V	3.3 V	-	3.3 V	3.3 V
筛选级别	-	-	-	MIL-PRF-38535 Class Q	MIL-PRF-38535 Class V	MIL-PRF-38535 Class V	MIL-PRF-38535 Class V