HSP45106
Data Sheet
October 1999
File Number
2809.5
16-Bit Numerically Controlled Oscillator
The Intersil HSP45106 is a high performance 16-bit
quadrature Numerically Controlled Oscillator (NCO16). The
NCO16 simplifies applications requiring frequency and
phase agility such as frequency-hopped modems, PSK
modems, spread spectrum communications, and precision
signal generators. As shown in the block diagram, the
HSP45106 is divided into a Phase/Frequency Control
Section (PFCS) and a Sine/Cosine Section.
The inputs to the Phase/Frequency Control Section consist
of a microprocessor interface and individual control lines.
The frequency resolution is 32 bits, which provides for
resolution of better than 0.008Hz at 33MHz. User
programmable center frequency and offset frequency
registers give the user the capability to perform phase
coherent switching between two sinusoids of different
frequencies. Further, a programmable phase control register
allows for phase control of better than 0.006
o
. In applications
requiring up to 8-level PSK, three discrete inputs are
provided to simplify implementation.
The output of the PFCS is a 28-bit phase which is input to
the Sine/Cosine Section for conversion into sinusoidal
amplitude. The outputs of the Sine/Cosine Section are two
16-bit quadrature signals. The spurious free dynamic range
of this complex vector is greater than 90dBc.
For added flexibility when using the NCO16 in conjunction
with DAC’s, a choice of either parallel or serial outputs with
either two’s complement or offset binary encoding is
provided. In addition, a synchronization signal is available
which indicates serial word boundaries.
Features
• 25.6MHz, 33MHz Versions
• 32-Bit Center and Offset Frequency Control
• 16-Bit Phase Control
• 8 Level PSK Supported Through Three Pin Interface
• Simultaneous 16-Bit Sine and Cosine Outputs
• Output in Two’s Complement or Offset Binary
• <0.008Hz Tuning Resolution at 33MHz
• Serial or Parallel Outputs
• Spurious Frequency Components <-90dBc
• 16-Bit Microprocessor Compatible Control Interface
Applications
• Direct Digital Synthesis
• Quadrature Signal Generation
• Spread Spectrum Communications
• PSK Modems
• Modulation - FM, FSK, PSK (BPSK, QPSK, 8PSK)
• Frequency Hopping Communications
• Precision Signal Generation
• Related Products
- Use with Data Acquisition Parts HI5731 or HI5741
Ordering Information
PART NUMBER
HSP45106JC-25
HSP45106JI-25
HSP45106JC-33
HSP45106GC-33
TEMP.
RANGE (
o
C)
0 to 70
-40 to 85
0 to 70
0 to 70
PACKAGE
84 Ld PLCC
84 Ld PLCC
84 Ld PLCC
85 Ld CPGA
PKG. NO.
N84.1.15
N84.1.15
N84.1.15
G85.A
Block Diagram
MICROPROCESSOR
INTERFACE
CLOCK
DISCRETE
CONTROL SIGNALS
SIN/COS
ARGUMENT
32
PHASE/
FREQUENCY
CONTROL
SECTION
SINE/
COSINE
SECTION
SINE
16
COSINE 16
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
HSP45106
Pinouts
85 PIN CPGA
TOP VIEW
11
L
GND
10
SIN0
9
SIN1
8
SIN3
7
SIN5
6
SIN4
5
SIN9
4
SIN12
3
SIN13
2
SIN14
1
DAC
STRB
COS0
L
K
BINFMT
V
CC
PAR/
SER
PACI
INITT
ENPO
REG
GND
TEST
CLK
SIN2
V
CC
SIN6
SIN8
SIN10
GND
SIN15
OES
K
J
INITPAC
EN
PHAC
ENTI
REG
ENCF
REG
CS
V
CC
MOD2
SIN7
SIN11
OEC
COS1
J
H
G
COS2
COS3
H
INHOF
ENOF
REG
WR
COS6
COS4
COS5
G
F
E
D
COS7
COS8
V
CC
F
E
COS11 COS10 COS9
GND
COS12 D
C
MOD0
C10
C9
C6
INDEX
COS15 COS13 C
PIN
C4
C1
TICO
COS14 B
B
MOD1
A2
A1
C15
C12
C13
V
CC
C0
5
A
PMSEL
11
A0
10
GND
9
C0
8
C0
7
C0
6
C0
4
C0
3
C2
2
C0
1
A
PIN ‘A1’
ID
85 PIN CPGA
BOTTOM VIEW
1
L
DAC
STRB
COS0
2
SIN14
3
4
5
SIN9
6
SIN4
7
SIN5
8
9
10
SIN0
11
GND
L
SIN13 SIN12
SIN3 SIN1
K
OES
SIN15
GND
SIN10
SIN8
V
CC
SIN6
SIN2 CLK
V
CC
PAR/
SER
PACI
BINFMT K
J
COS1
OEC
SIN11
SIN7
INITPAC J
EN
PHAC
ENTI
REG
ENCF
REG
CS
V
CC
MOD2
H
COS3
COS2
H
G
G
COS5
COS4
COS6
INHOF
ENOF
REG
WR
INITT
ENPO
REG
GND
TEST
F
E
V
CC
COS8
COS7
F
E
D
COS9 COS10 COS11
D COS12
GND
INDEX
PIN
C1
C4
C COS13 COS15
C6
C9
C10
MOD0
C
B COS14
TICO
V
CC
C0
5
C13
C12
C15
A1
A2
MOD1
B
A
PIN ‘A1’
ID
C0
1
C2
2
C0
3
C0
4
C0
6
C0
7
C0
8
GND
9
A0
10
PMSEL
11
A
2
HSP45106
Pinouts
(Continued)
84 LEAD PLCC
TOP VIEW
C0
C1
C2
C3
C4
C5
C6
V
CC
C7
C8
C9
C10
C11
C12
C13
C14
C15
GND
A0
A1
A2
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
TICO
COS15
COS14
COS13
GND
COS12
COS11
COS10
COS9
COS8
COS7
COS6
COS5
COS4
V
CC
COS3
COS2
COS1
COS0
OEC
DACSTRB
PMSEL
MOD0
MOD1
MOD2
TEST
V
CC
WR
GND
CS
ENCFREG
ENOFREG
INHOFR
ENTIREG
INITTAC
ENPOREG
INPHAC
PACI
INITPAC
BINFMT
PAR/SER
V
CC
Pin Descriptions
NAME
V
CC
GND
C(15:0)
A(2:0)
CS
WR
CLK
ENPOREG
I
I
I
I
I
I
TYPE
+5 power supply pin.
Ground.
Control input bus for loading phase, frequency, and timer data into the PFCS. C0 is LSB.
Address pins for selecting destination of C(15:0) data (Table 2). A0 is the LSB
Chip select (active low). Enables data to be written into Control Registers by WR.
Write enable (active low). Data is clocked into the register selected by A(2:0) on the rising edge of WR when CS
is low.
Clock. All registers, except the Control Registers clocked with WR, are clocked (when enabled) by the rising edge
of CLK.
Phase Offset Register Enable (active low). Registered on chip by CLK. When active, after being clocked onto chip,
ENPOREG enables the clocking of data into the Phase Offset Register. Allows ROM address to be updated
regardless of ENPHAC.
Offset Frequency Register Enable (active low). Registered on chip by CLK. When active, after being clocked onto
chip, ENOFREG enables the clocking of data into the Offset Frequency Register.
Center Frequency Register Enable (active low). Registered on chip by CLK. When active, after being clocked onto
chip, ENCFREG enables the clocking of data into the Center Frequency Register.
Phase Accumulator Register Enable (active low). Registered on chip by CLK. When active, after being clocked onto
chip, ENPHAC enables the clocking of data into the Phase Accumulator Register.
Timer Increment Register Enable (active low). Registered on chip by CLK. When active, after being clocked onto
chip, ENTIREG enables the clocking of data into the Timer Increment Register.
Inhibit Offset Frequency Register Output (active low). Registered on chip by CLK. When active, after being clocked
onto chip, INHOFR zeroes the data path from the Offset Frequency Register to the Frequency Adder. New data
can be still clocked into the Offset Frequency Register. INHOFR does not affect the contents of the register.
Initialize Phase Accumulator (active low). Registered on chip by CLK. Zeroes the feedback path in the Phase
Accumulator. Does not clear the Phase Accumulator Register.
Modulation Control Inputs. When selected with the PMSEL line, these bits add an offset of 0, 45, 90, 135, 180,
225, 270, or 315 degrees to the current phase (i.e., modulate the output). The lower 13 bits of the phase control
are set to zero. These bits are registered when the Phase Offset Register is enabled.
DESCRIPTION
ENOFREG
ENCFREG
ENPHAC
ENTIREG
INHOFR
I
I
I
I
I
INITPAC
MOD(2:0)
I
I
3
OES
SIN15
SIN14
SIN13
GND
SIN12
SIN11
SIN10
SIN9
SIN8
SIN7
SIN6
SIN5
V
CC
SIN4
SIN3
SIN2
SIN1
SIN0
CLK
GND
HSP45106
Pin Descriptions
NAME
PMSEL
TYPE
I
(Continued)
DESCRIPTION
Phase Modulation Select input. Registered on chip by CLK. This input determines the source of the data clocked
into the Phase Offset Register. When high, the Phase Input Register is selected. When low, the external
modulation pins (MOD(2:1)) control the three most significant bits of the Phase Offset Register and the 13 least
significant bits are set to zero.
Phase Accumulator Carry Input (active low). Registered on chip by CLK.
Initialize Timer Accumulator (active low). This input is registered on chip by CLK. When active, after being clocked
onto chip, INITTAC enables the clocking of data into the Timer increment Register, and also zeroes the feedback
path in the Timer Accumulator.
Test Select Input. Registered on chip by CLK. This input is active high. When active, this input enables test busses
to the outputs instead of the sine and cosine data.
Parallel/Serial Output Select. This input is registered on chip by CLK. When low, the sine and cosine outputs are
in serial mode. The Output Shift Registers will load in new data after ENPHAC goes low and will start shifting the
data out after ENPHAC goes high. When this input is high, the Output Registers are loaded every clock and no
shifting takes place.
Format. This input is registered on chip by CLK. When low, the MSB of the SIN and COS are inverted to form an
offset binary (unsigned) number.
Three-state control for bits SIN(15:0). Outputs are enabled when OES is low.
Three-state control for bits COS(15:0). Outputs are enabled when OEC is low.
Timer Accumulator Carry Output. Active low, registered. This output goes low when a carry is generated by the
Timer Accumulator.
DAC Strobe (active low). In serial mode, this output will go low when the first bit of a new output word is valid at
the shift register output. This pin is active only in serial mode.
Sine Output Data. When parallel mode is enabled, data is output on SIN(15:0). When serial mode is enabled,
output data bits are shifted out of SIN15 and SIN0. The bit stream on SIN15 is provided MSB first while the bit
stream on SIN0 is provided LSB first.
Cosine Output Data. When parallel mode is enabled, data is output on COS(15:0). When serial mode is enabled,
output data bits are shifted out of COS15 and COS0. The bit stream on COS15 is provided MSB first while the bit
stream in COS0 is provided LSB first.
Used to align chip in socket or on circuit board. Must be left as a no connect in circuit. (CPGA Package only).
PACI
INITTAC
I
I
TEST
PAR/SER
I
I
BINFMT
OES
OEC
TICO
DACSTRB
SIN(15:0)
I
I
I
O
O
O
COS(15:0)
O
Index Pin
Functional Description
The 16-bit Numerically Controlled Oscillator (NCO16)
produces a digital complex sinusoid waveform whose
frequency and phase are controlled through a standard
microprocessor interface and discrete inputs. The NCO16
generates 16-bit sine and cosine vectors at a maximum
sample rate of 33MHz. The NCO16 can be preprogrammed
to produce a constant (CW) sine and cosine output for Direct
Digital Synthesis (DDS) applications. Alternatively, the
phase and frequency inputs can be updated in real time to
produce a FM, PSK, FSK, or MSK modulated waveform. To
simplify PSK generation, a 3 pin interface is provided to
support modulation of up to 8 levels.
As shown in Figure 1, the HSP45106 Block Diagram, the
NCO16 is comprised of a Phase and Frequency Control
Section (PFCS) and Sine/ Cosine Section. The PFCS stores
the phase and frequency control inputs and uses them to
calculate the phase angle of a rotating complex vector. The
Sine/Cosine Section performs a lookup on this phase and
generates the appropriate amplitude values for the sine and
cosine. These quadrature outputs may be configured as
serial or parallel with either two's complement or offset
binary format.
Phase/Frequency Control Section
The phase and frequency of the quadrature outputs are
controlled by the PFCS (Figure 1). The PFCS generates a
32-bit word which represents the instantaneous phase
(Sin/Cos argument) of the sine and cosine waves being
generated. This phase is incremented on the rising edge of
each CLK by the preprogrammed amounts in the phase and
Frequency Control Registers. As the instantaneous phase
steps from 0 through full scale (2
32
- 1), the phase of the
quadrature outputs proceeds from 0
o
around the unit circle
counter clockwise.
The PFCS is comprised of a Phase Accumulator Section,
Phase Offset adder, Input Section, and a Timer Accumulator
Section. The Phase Accumulator computes the
instantaneous phase angle from user programmed values in
the Center and Offset Frequency Registers. This angle is
then fed into the Phase Offset adder where it is offset by the
preprogrammed value in the Phase Offset Register. The Input
Section routes data from a microprocessor compatible control
bus and discrete input signals into the appropriate configuration
registers. The Timer Accumulator supplies a pulse to mark the
passage of a user programmed period of time.
4
OES
OEC
/
20
/
ADDRESS
DECODE
/
16 SIN
FORMAT
CONTROL 28
/
SIN/COS
ROM
/
/
OUTPUT
CONTROL
16 COS
16
16
SIN(15:0)
COS(15:0)
DACSTRB
SIN/COS ARGUMENT
16
PHASE INPUT
PHASE
INPUT REG (16)
16
13
'0'
16
R.PMSEL
CENTER
FREQUENCY
16
CLK >
R.ENCFREG
R
E
G
32
CENTER
FREQUENCY
32 REGISTER
0
MUX
ENCODER
R
E
G
MSB CENTER
FREQUENCY INPUT
REG (16)
16
R
E
G
LSB
CENTER
FREQUENCY
INPUT REG (16)
FREQUENCY
ADDER
32
32
R
E
G
CLK
32
1
1
32
MUX
32
0
'0'
32
MUX
0
A
D
D
E
R
>
32
3
1
R.ENPHAC
TEST
3
PAR/SER
BINFMT
INPUT SECTION (DISCRETE CONTROL INPUT SIGNALS
AND PROCESSOR CONTROL INTERFACE)
C(15:0)
WR
PHEN
>
R
E
G
1
0
INHOFR
R.INHOFR
MUX
5
WR
>
WR >
LSCFEN
R
E
G
MSB OFFSET
FREQUENCY INPUT
REG (16)
16
R
E
G
LSB OFFSET
FREQUENCY
INPUT REG (16)
16
MSB TIMER INCREMENT
INPUT REG (16)
16
LSB TIMER
INCREMENT INPUT
REG (16)
WR
>
A
D
D
E
R
WR
LSOFEN
R
E
G
>
OFFSET FREQUENCY
REGISTER
OFFSET
32
R
FREQUENCY 32
E
32
G
CLK >
'0'
R.ENOFREG
R.INHOFR
WR >
MSTIEN
WR
LSTIEN
>
R
E
G
R.INITPAC
R.PACI
TIMER
INCREMENT 32
R
E
G
>
TIMER
INCREMENT CLK
REGISTER
R.ENTIREG
R.INITTAC
32
32
32
'0'
32
A
D
D
E
R
R.INITTAC
MOD(2:1)
28
R
E
G
>
WR
PHEN
CS
MSCFEN
PHASE OFFSET
PHASE OFFSET
ADDER
REGISTER
16
16
A
R
16
D
E
D
16
G
E LSBs 16
CLK >
R
MSBs
CLK
R.ENPOREG
A(2:0)
D
E
C
O
D
E
LSCFEN
MSOFEN
LSOFEN
MSTIEN
LSTIEN
HSP45106
PHASE
ACCUMULATOR
REGISTER
PHASE
ACCUMULATOR
SECTION
R.ENPHAC
32
32
R
E
G
CLK
>
PMSEL
R.PMSEL
ENCFREG
R.ENCFREG
ENPOREG
R.ENPOREG
ENOFREG
R.ENOFREG
INITPAC
PACI
R
E
G
R.INITPAC
CLK
TIMER
ACCUMULATOR
SECTION
>
R
E
G
TICO
R.PACI
ENPHAC
R.ENPHAC
ENTIREG
R.ENTIREG
INITTAC
R.INITTAC
CLK
>
CLK
FIGURE 1. BLOCK DIAGRAM OF THE HSP45106
