®
HSP48901
Data Sheet
July 2004
FN2459.6
3 x 3 Image Filter
The Intersil HSP48901 is a high speed 9-Tap FIR Filter
which utilizes 8-bit wide data and coefficients. It can be
configured as a one-dimensional (1-D) 9-Tap filter for a
variety of signal processing applications, or as a two
dimensional (2-D) filter for image processing. In the 2-D
configuration, the device is ideally suited for implementing 3
x 3 kernel convolution. The 30MHz clock rate allows a large
number of image sizes to be processed within the required
frame time for real-time video.
Data is provided to the HSP48901 through the use of
programmable data buffers such as the HSP9500 or any
other Programmable Shift Register. Coefficient and pixel
input data are 8-bit signed or unsigned integers, and the
20-bit extended output guarantees no overflow will occur
during the filtering operation.
There are two internal register banks for storing independent
3 x 3 filter kernels, thus, facilitating the implementation of
adaptive filters and multiple filter operations on the same
data.
The configuration of the HSP48901 Image Filter is controlled
through a standard microprocessor interface and all inputs
and outputs are TTL compatible.
Features
• DC to 30MHz Clock Rate
• Configurable for 1-D and 2-D Correlation/Convolution
• Dual Coefficient Mask Registers, Switchable in a Single
Clock Cycle
• Two’s Complement or Unsigned 8-Bit Input Data and
Coefficients
• 20-Bit Extended Precision Output
• Standard
µP
Interface
Applications
• Image Filtering
• Edge Detection/Enhancement
• Pattern Matching
• Real Time Video Filters
Ordering Information
PART NUMBER
HSP48901JC-30
TEMP.
RANGE (°C)
0 to 70
PACKAGE
68 Ld PLCC
PKG.
DWG. #
N68.95
Block Diagram
DIN3 (0-7)
DIN2 (0-7)
DIN1 (0-7)
Z
-1
Z
-1
Z
-1
MODE
CIN0-7
FRAME
Z
-1
Z
-1
A0-2
LD
3
ADDRESS
DECODER
INTERNAL
CLOCK
CLK
HOLD
CLOCK
GEN
I
H
G
Z
-1
F
E
D
2:1
Z
-1
Z
-1
Z
-1
C
B
A
MODE
2:1
Z
-1
Z
-1
Z
-1
CONTROL
LOGIC
Z
-1
Z
-1
+
Z
-1
Z
-1
Z
-1
+
Z
-1
+
Z
-1
Z
-1
Z
-1
Z
-1
+
Z
-1
DOUT 0-19
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright Harris Corporation 1999, Copyright Intersil Americas Inc. 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HSP48901
Pinouts
68 LEAD PLCC
TOP VIEW
V
CC
DIN1 (0)
DIN1 (1)
DIN1 (2)
DIN1 (3)
DIN1 (4)
DIN1 (5)
DIN1 (6)
DIN1 (7)
GND
DOUT0
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
V
CC
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
DIN2 (7)
DIN2 (6)
DIN2 (5)
DIN2 (4)
DIN2 (3)
DIN2 (2)
DIN2 (1)
DIN2 (0)
GND
DIN3 (7)
DIN3 (6)
DIN3 (5)
DIN3 (4)
DIN3 (3)
DIN3 2)
DIN3 (1)
DIN3 (0)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
V
CC
CLK
GND
CIN7
CIN6
CIN5
CIN4
CIN3
CIN2
CIN1
CIN0
GND
LD
HOLD
A2
A1
A0
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
DOUT6
DOUT7
DOUT8
DOUT9
GND
DOUT10
DOUT11
DOUT12
DOUT13
DOUT14
DOUT15
DOUT16
DOUT17
DOUT18
DOUT19
V
CC
FRAMES
Pin Descriptions
NAME
V
CC
GND
CLK
DIN1(7-0)
PLCC PIN
9, 27, 45, 61
18, 29, 38, 56
28
1-8
I
I
TYPE
DESCRIPTION
The +5V power supply pins. 0.1µF capacitors between the V
CC
and GND pins are
recommended.
The device ground.
Input and System clock. Operations are synchronous with the rising edge of this clock signal.
Pixel Data Input Bus #1. These inputs are used to provide 8-bit pixel data to the HSP48901. The data must be
provided in a synchronous fashion, and is latched on the rising edge of the CLK signal. The DIN1(0-7) inputs
are also used to input data when operating in the 9-Tap FIR mode.
Pixel Data Input Bus #2. Same as above. These inputs should be grounded when operating in the 1D mode.
Pixel Data Input Bus #3. Same as above. These inputs should be grounded when operating in the 1D mode.
Coefficient Data Input Bus. This input bus is used to load the Coefficient Mask Register(s) and the Initialization
Register. The register to be loaded is defined by the register address bits A0-2. The CIN0-7 data is loaded to
the addressed register through the use of the LD input.
Output Data Bus. This 20-Bit output port is used to provide the convolution result. The result is the sum of
products of the input data samples and their corresponding coefficients.
FRAME is an asynchronous new frame or vertical sync input. A low on this input resets all internal circuitry
except for the Coefficient and INT Registers. Thus, after a FRAME reset has occurred, a new frame of pixels
may be convolved without reloading these registers.
The Hold Input is used to gate the clock from all of the internal circuitry of the HSP48901. This signal is
synchronous, is sampled on the rising edge of CLK and takes effect on the following cycle. While this signal is
active (high), the clock will have no effect on the HSP48901 and internal data will remain undisturbed.
Control Register Address. These lines are decoded to determine which register in the control logic is the
destination for the data on the CIN0-7 inputs. Register loading is controlled by the A0-2 and LD inputs.
Load Strobe. LD is used for loading the Internal Registers of the HSP48901. The rising edge of LD will latch
the CIN0-7 data into the register specified by A0-2. The Address on A0-2 must be setup with respect to the
falling edge of LD and must be held with respect to the rising edge of LD.
DIN2(7-0)
DIN3(7-0)
CIN7-0
10-17
19-26
30-37
I
I
I
DOUT19-0 46-55, 57-60,
62-67
FRAME
44
O
I
HOLD
40
I
A2-0
LD
41-43
39
I
I
2
HSP48901
Functional Description
The HSP48901 can perform convolution of a 3 x 3 filter kernel
with 8-bit image data. It accepts the image data in a raster
scan, non-interlaced format, convolves it with the filter kernel
and outputs the filtered image. The input and filter kernel data
are both 8-bits, while the output data is 20 bits to prevent
overflow during the convolution operation. Image data is input
via the DIN1, DIN2, and DIN3 busses. This data would
normally be provided by programmable data buffer such as
the HSP9501 as illustrated in the Operations Section of this
specification. The data is then convolved with the 3 x 3 array
of filter coefficients. The resultant output data is then stored in
the Output Register. The HSP48901 may also be used in a
one-dimensional mode. In this configuration, it functions as a
1-D 9-tap FIR filter. Data would be input via the DIN1(0-7) bus
for operation in this mode.
Initialization of the convolver is done using the CIN0-7 bus to
load configuration data and the filter kernel(s). The address
lines A0-2 are used to address the Internal Registers for
initialization. The configuration data is loaded using the
A0-2, CIN0-7 and LD controls as address, data and write
enable, respectively. This interface is compatible with
standard microprocessors without the use of any additional
glue logic.
Filtered image data is output from the convolver over the
DOUT0-19 bus. This output bus is 20 bits wide to provide
room for growth during the convolution operation.
8-Bit Multiplier Array
The multiplier array consists of nine 8 x 8 multipliers. Each
multiplier forms the product of a filter coefficient with a
corresponding pixel in the input image. Input and coefficient
data may be in either two's complement or unsigned integer
format. The nine coefficients form a 3 x 3 filter kernel which
is multiplied by the input pixel data and summed to form a
sum of products for implementation of the convolution
operation as shown below:
FILTER KERNEL
A
D
G
B
E
H
C
F
I
P1
P4
P7
INPUT DATA
P2
P5
P8
P3
P6
P9
OUTPUT = (A x P1) + (B x P2) + (C x P3)
+ (D x P4) + (E x P5) + (F x P6)
+ (G x P7) + (H x P8) + (I x P9)
Control Logic
The control logic (Figure 1) contains the Initialization
Register and the Coefficient Registers. The control logic is
updated by placing data on the CIN0-7 bus and using the
A0-2 and LD control lines to write to the addressed register
(see Address Decoder). All of the Control Logic Registers
are unaffected by FRAME.
3
A0 - 2
ADDRESS
CODE
LD
ENCRO
ENCR1
CAS
CR1
CRO
CIN0 - 7
INITIALIZATION REGISTER
(INT)
INITIALIZATION
DATA
CAS
COEFFICIENT
REGISTER 0
I0
E
H0
E
G0
E
F0
E
E0
E
D0
E
C0
E
B0
E
A0
E
CR0
I
H
G
F
E
D
C
B
A
CR1
ENCR1
ENCR0
S
C
Q
Q
I1
E
H1
E
G1
E
F1
E
E1
E
D1
E
C1
E
B1
E
A1
E
COEFFICIENT
REGISTER 1
FIGURE 1. CONTROL LOGIC BLOCK DIAGRAM
3
HSP48901
Initialization Register
The Initialization Register is used to appropriately configure
the convolver for a particular application. It is loaded through
the use of the CIN0-7 bus along with the LD input. Bit-0
defines the input data and coefficients format (unsigned or
two's complement); Bit-1 defines the mode of operation (1-D
or 2-D); and Bit-2 and Bit-3 determine the type of rounding to
occur on the DOUT0-19 bus; The complete definition of the
Initialization Register bits is given in Table 1.
TABLE 1. INITIALIZATION REGISTER
INITIALIZATION REGISTER
BIT 0
0
1
BIT 1
0
1
3 BIT 2
0
0
1
1
0
1
0
1
FUNCTION = INPUT AND COEFFICIENT
DATA FORMAT
Unsigned Integer Format
Two’s Complement Format
FUNCTION = OPERATING MODE
1-D 9-Tap Filter
2-D 3 x 3 Filter
FUNCTION = OUTPUT ROUNDING
No Rounding
Round to 16 Bits (i.e., DOUT19-4)
Round to 8 Bits (i.e., DOUT19-12)
Not Valid
The nine coefficients must be loaded sequentially over the
CIN0-7 bus from A to I. The address of CREG0 or CREG1 is
placed on A0-2, and then the coefficients are written to the
corresponding Coefficient Register one at a time by using
the LD input.
Address Decoder
The address decoder (see Figure 1) is used for writing to the
control logic of the HSP48901. Loading an Internal Register
is done by selecting the Destination Register with the A0-2
address lines, placing the data on CIN0-7, and asserting LD
control line. When LD goes high, the data on ClN0-7 is
latched into the addressed register. The address map for the
A0-2 bus is shown in Table 2.
While loading of the control logic registers is asynchronous
to CLK, the target register in the control logic is being read
synchronous to the internal clock. Therefore, care must be
taken when modifying the convolver setup parameters
during processing to avoid changing the contents of the
registers near a rising edge of CLK. The required setup time
relative to CLK is given by the specification TLCS. For
example, in order to change the active coefficient register
from CREG0 to CREG1 during an active convolution
operation, a write will be performed to the address for
selecting CREG1 for internal processing (A0-2 = 110). In
order to provide proper uninterrupted operation, LD should
be deasserted at least TLCS prior to the next rising edge of
CLK. Failure to meet this setup time may result in
unpredictable results on the output of the convolver. Keep in
mind that this requirement applies only to the case where
changes are being made in the control logic during an active
convolution operation. In a typical convolver configuration
routine, where the configuration data is loaded prior to the
actual convolution operation, this specification would not
apply.
TABLE 2. ADDRESS MAPS
CONTROL LOGIC ADDRESS MAP
A2-0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
FUNCTION
Reserved for Future Use.
Reserved for Future Use.
Load Coefficient Register 0 (CREG0).
Load Coefficient Register 1 (CREG1).
Load Initialization Register (INT).
Select CREG0 for Internal Processing.
Select CREG1 for Internal Processing.
No Operation.
Coefficient Registers (CREG0, CREG1)
The control logic contains two coefficient register banks,
CREG0 and CREG1. Each of these register banks is
capable of storing nine 8-bit filter coefficient values (3 x 3
Kernel). The output of the registers are connected to the
coefficient input of the corresponding multiplier in the 3 x 3
multiplier array (designated A through I). The register bank
to be used for the convolution is selectable by writing to the
appropriate address (see address decoder). All registers in a
given bank are enabled simultaneously, and one of the
banks is always active.
For most applications, only one of the register banks is
necessary. The user can simply load CREG0 after power up,
and use it for the entire convolution operation. (CREG0 is
the Default Register). The alternate register bank allows the
user to maintain two sets of filter coefficients and switch
between them in real time. The coefficient masks are loaded
via the CIN0-7 bus by using A0-2 and LD. The selection of
the particular register bank to be used in processing is also
done by writing to the appropriate address (See address
decoder). For example, if CREG0 is being used to provide
coefficients to the multipliers, CREG1 can be updated at a
low rate by an external processor; then, at the proper time,
CREG1 can be selected, so that the new coefficient mask is
used to process the data. Thus, no clock cycles have been
lost when changing between alternate 3 x 3 filter kernels.
4
HSP48901
Control Signals
HOLD
The HOLD control input provides the ability to disable
internal clock and stop all operations temporarily. HOLD is
sampled on the rising edge of CLK and takes effect during
the following clock cycle (refer to Figure 2). This signal can
be used to momentarily ignore data at the input of the
convolver while maintaining its current output data and
operational state.
CLK
Register. The coefficients can now be loaded one at a time
from A to I via the CIN0-7 coefficient bus, and the A0-2 and
LD control lines.
IMAGE
DATA
8
DIN 1 (0 -7)
20
DOUT 0 -19
DATA
BUFFER
DATA
BUFFER
INITIALIZATION
DATA
A
D
F
B
E
H
C
F
I
P
M -1, N -1
P
M, N -1
P
M+1, N -1
P
M -1, N
P
M, N
P
M+1, N
IMAGE DATA
P
M -1, N +1
P
M, N +1
P
M+1, N +1
DIN 2 (0 -7)
HSP48901
DIN 3 (0 -7)
FILTERED
IMAGE
DATA
HOLD
INTERNAL
CLOCK
FILTER KERNEL
FIGURE 2. HOLD OPERATION
FIGURE 3. 3 x 3 KERNEL ON AN 8-BIT IMAGE
FRAME
The FRAME input initializes all internal flip flops and
registers except for the coefficient and Initialization
Registers. It is used as a reset between video frames and
eliminates the need to reinitialize the entire HSP48901 or
reload the coefficients. The registers and flip flops will
remain in a reset state as long as FRAME is active. FRAME
is an asynchronous input and may occur at any time.
However, it must be deasserted at least t
FS
ns prior to the
rising clock edge that is to begin operation for the next frame
in order to ensure the new pixel data is properly loaded.
Operation
A single HSP48901 can be used to perform 3 x 3 convolution
on 8-bit image data. A Block Diagram of this configuration is
shown in Figure 3. The inputs of an external data buffer (such
as the HSP9501) are connected to the input data in parallel
with the DlN1(0-7) lines; the outputs of the data buffer are
connected to the DIN2(0-7) bus. A second external data
buffer is connected between the outputs of the first buffer and
the DIN3(0-7) inputs. To perform the convolution operation, a
group of nine image pixels is multiplied by the 3 x 3 array of
filter coefficients and their products are summed and sent to
the output. For the example in Figure 3, the pixel value in the
output image at location m, n is given by:
DOUT(m,n) = A x Pm-1, n-1 + B x Pm-1,n
+ D x Pm, n-1
+ E x Pm, n
+C x Pm-1, n+1
+ F x Pm, n+1
Multiple filter kernels can also be used on the same image
data using the dual Coefficient Registers CREG0 and
CREG1. This type of filtering is used when the characteristics
of the input pixel data change over the image in such a way
that no one filter produces satisfactory results for the entire
image. In order to filter such an image, the characteristics of
the filter itself must change while the image is being
processed. The HSP48901 can perform this function with the
use of an external processor. The processor is used to
calculate the required new filter coefficients, loads them into
the Coefficient Register not in use, and selects the newly
loaded Coefficient Register at the proper time. The first
Coefficient Register can then be loaded with new coefficients
in preparation for the next change. This can be carried out
with no interruption in processing, provided that the new
register is selected synchronous to the convolver CLK signal.
The HSP48901 can also operate as a one dimensional 9-tap
FIR filter by programming the Initialization Register to 1-D
mode (i.e., INT bit-1 = 0). This configuration will provide for
nine sequential input values to be multiplied by the coefficient
values in the selected Coefficient Register and provide the
proper filtered output. The input bus to be used when
operating in this mode is the DIN1(0-7) inputs.
The equation for the output in the 1-D 9-tap FIR case
becomes:
D0UTn = A x Dn-8 + B x Dn-7 + C x Dn-6 + D x Dn-5
+ E x Dn-4 + F x Dn-3 + G x Dn-2 + H x Dn-1
+ l x Dn
+ G x Pm+1,n-1 + H x Pm+1,n +I xPm+1, n+1
This process is continually repeated until the last pixel of the
last row of the image has been input. It can then start again
with the first row of the next frame. The FRAME pin is used to
clear the Internal Multiplier Registers and DOUT0-19
Registers between frames. The row length of the image to be
convolved is limited only by the maximum length of the
external data buffers.
The setup is straightforward. The user must first setup the
HSP48901 by loading a new value into the Initialization
5
Frame Rate
The total time to process an image is given by the formula:
T = R x C/F, where:
T = Time to process a frame
R = Number of rows in the image
C = Number of pixels in a row
F = Clock rate of the HSP48901
FPGA/CPLD
