Calling Line Identification Receiver
Features
·
·
·
·
HT9032
HT9032B/C/D operating voltage: 3.5V~5.5V
HT9032F operating voltage: 3.0V~5.5V
Bell 202 FSK and V.23 demodulation
Ring detection input and output
Carrier detection output
·
·
·
Power down mode
High input sensitivity
HT9032C: 16-pin DIP/SOP package
HT9032B/F-A: 8-pin DIP package
HT9032D/F-B: 8-pin SOP package
Applications
·
·
·
Feature phones
Caller ID adjunct boxes
Fax and answering machines
·
·
Computer telephony interface products
ADSI products
General Description
The HT9032 calling line identification receiver
is a low power CMOS integrated circuit de-
signed for receiving physical layer signals tran-
smitted according to Bellcore TR-NWT-000030
and ITU-T V.23 specifications. The primary ap-
plication of this device is for products used to
receive and display the calling number, or mes-
sage waiting indicator sent to subscribers from
the central office facilities. The device also pro-
vides a carrier detection circuit and a ring de-
tection circuit for easier system applications.
1
April 6, 2000
HT9032
Block Diagram
T IP
R IN G
B a n d P a s s
F ilte r
D e m o d u la to r
P D W N
P o w e r U p
L o g ic
V a lid D a ta
D e te c tio n
D O U T C
D O U T
C D E T
R T IM E
In te rn a l
P o w e r U p
L o g ic
R D E T 1
R D E T 2
R in g
A n a ly s is
C ir c u it
R D E T
V D D
V S S
R e fe re n c e
V o lta g e
C lo c k
G e n e ra to r
X 1
X 2
Pin Assignment
T IP
R IN G
2
3
4
5
6
7
8
R D E T 1
R D E T 2
T IP
R IN G
P D W N
3
6
4
5
V S S
2
7
1
8
V D D
D O U T
X 1
X 2
N C
R T IM E
P D W N
V S S
1
1 6
1 5
1 4
1 3
1 2
1 1
1 0
9
V D D
D O U T C
D O U T
C D E T
R D E T
N C
X 1
X 2
D O U T
V D D
T IP
3
6
4
5
R IN G
2
7
1
8
X 1
X 2
V S S
P D W N
H T 9 0 3 2 B
8 D IP
H T 9 0 3 2 C
1 6 D IP /S O P
H T 9 0 3 2 D
8 S O P
T IP
R IN G
P D W N
3
V S S
4
2
1
8
7
6
5
V D D
D O U T
C D E T
X 1
D O U T
V D D
T IP
3
R IN G
4
2
1
8
7
6
5
C D E T
X 1
V S S
P D W N
H T 9 0 3 2 F -A
8 D IP
H T 9 0 3 2 F -B
8 S O P
2
April 6, 2000
HT9032
Pin Description
Pin Name I/O
Power Inputs
VDD
VSS
PDWN
Clock
X1
X2
I
O
A crystal or ceramic resonator should be connected to this pin and X2.
This pin may be driven from an external clock source.
A crystal or ceramic resonator should be connected to this pin and X1.
It detects ring energy on the line through an attenuating network and enables
the oscillator and ring detection. This is a schmitt trigger input.
It couples the ring signal to the precision ring detector through an attenuating
network. RDET=²0² if a valid ring signal is detected. This is a schmitt trigger in-
put.
¾
¾
I
Power-VDD is the input power for the internal logic.
Ground-VSS is ground connection for the internal logic.
A logic
²1²
on this pin puts the chip in power down mode. When a logic
²0²
is on
this pin, the chip is activated. This is a schmitt trigger input.
Description
Ring Detections
RDET1
RDET2
I
I
RTIME
An RC network may be connected to this pin in order to hold the pin voltage be-
low 2.2V between the peaks of the ringing signal. This pin controls internal
I/O power up and activates the partial circuitry needed to determine whether the
incoming ring is valid or not. The input is a schmitt trigger input. The output
cell structure is an NMOS output.
This input pin is connected to the tip side of the twisted pair wires. It is inter-
nally biased to 1/2 V
DD
when the device is in power up mode. This pin must be
DC isolated from the line.
This input pin is connected to the ring side of the twisted pair wires. It is inter-
nally biased to 1/2 V
DD
when the device is in power up mode. This pin must be
DC isolated from the line.
This open drain output goes low when a valid ringing signal is detected. When
connected to PDWN pin, this pin can be used for auto power up.
This open drain output goes low indicating that a valid carrier is present on the
line. A hysteresis is built-in to allow for a momentary drop out of the carrier.
When connected to PDWN pin, this pin can be used for auto power up.
This pin presents the output of the demodulator whenever CDET pin is low.
This data stream includes the alternate
²1²
and
²0²
pattern, the marking, and
the data. At all other times, this pin is held high.
FSK Signal Inputs
TIP
I
RING
I
Detection Results
RDET
CDET
O
O
DOUT
O
3
April 6, 2000
HT9032
Pin Name I/O
DOUTC
O
Description
This output presents the output of the demodulator whenever CDET pin is low
and when an internal validation sequence has been successfully passed. This
data stream does not include the alternate
²1²
and
²0²
pattern. This pin is al-
ways held high.
Absolute Maximum Ratings
Voltages are referenced to V
SS
, except where noted.
Supply Voltage..............................-0.5V to 6.0V
Operating Temperature Range .......0°C to 70°C
All Input Voltages ....................................25mW
Storage Temperature Range .....-40°C to 150°C
Note: These are stress ratings only. Stresses exceeding the range specified under
²Absolute
Maxi-
mum Ratings² may cause substantial damage to the device. Functional operation of this device
at other conditions beyond those listed in the specification is not implied and prolonged expo-
sure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol
V
DD
I
DD1
I
DD2
Parameter
Supply Voltage
Supply Current
Supply Current
Test Conditions
V
DD
¾
5V
5V
Conditions
9032B/C/D
9032F
PDWN=0 (3.58MHz OSC on)
PDWN=1 and RTIME=0
(3.58MHz OSC on and
internal circuits
partially on)
PDWN=1 and RTIME=1
(3.58MHz OSC off)
¾
¾
I
OL
=1.6mA
I
OH
=0.8mA
¾
RDET1, RTIME, PDWN
Crystal=3.58MHz, Ta=0~70°C
Min.
3.5
3.0
¾
¾
Typ.
5
5
3.2
1.9
Max. Unit
5.5
5.5
5
2.5
V
V
mA
mA
I
STBY
V
IL
V
IH
I
OL
I
OH
I
IN
V
T-
Standby Current
Input Voltage Logic 0
Input Voltage Logic 1
Output Voltage Logic 0
Output Voltage Logic 1
Input Leakage Current,
All Inputs
Input Low Threshold
Voltage
5V
5V
5V
5V
5V
5V
5V
¾
¾
0.8V
0.9V
-1
2.0
¾
¾
¾
¾
¾
¾
2.3
1
0.2V
¾
0.1V
¾
1
2.6
mA
V
DD
V
DD
V
DD
V
DD
mA
V
4
April 6, 2000
HT9032
Symbol
V
T+
Parameter
Input High Threshold
Voltage
Input DC Resistance
Test Conditions
V
DD
5V
5V
5V
Conditions
RDET1, RTIME, PDWN
RDET2
TIP, RING
Min.
2.5
1.0
¾
Typ.
2.75
1.1
500
Max. Unit
3.0
1.2
¾
V
V
kW
V
TRDET2
Input Threshold Voltage
R
IN
T IP
R IN G
R D E T 1
R D E T 2
R T IM E
P D W N
V S S
~
V D D
D O U T C
D O U T
C D E T
R D E T
X 1
X 2
0 .1
m
F
H T 9 0 3 2 C
3 .5 8 M H z
1 0 M
W
3 0 p F
S u p p ly c u r r e n t te s tin g : A ll, e x c e p t P D W N a n d R T IM E ,
u n w ir e d p in s a r e le ft flo a tin g .
5
April 6, 2000
