Supertex inc.
32-Channel Serial to Parallel Converter
With High Voltage Push-Pull Outputs
Features
►
Processed with HVCMOS
®
technology
►
►
►
►
Low power level shifting
Source/sink current minimum 20mA
Shift register speed 8.0MHz
Latched data outputs
HV5308B
General Description
The HV5308B is a low voltage serial to high voltage parallel
converter with push-pull outputs. This device has been designed
for use as a driver for AC-electroluminescent displays. It can also
be used in any application requiring multiple output high voltage
current sourcing and sinking capabilities, such as driving plasma
panels, vacuum fluorescent, or large matrix LCD displays.
The HV5308B consists of a 32-bit shift register, 32 latches, and
control logic to enable outputs. Q1 is connected to the first stage
of the shift register through the Output Enable logic. Data is shifted
through the shift register on the low to high transition of the clock.
When viewed from the top of the package, the HV5308B shifts
in the clockwise direction. A data output buffer is provided for
cascading devices. This output reflects the current status of the
last bit of the shift register (32). Operation of the shift register is
not affected by the LE (latch enable) or the OE (output enable)
inputs. Transfer of data from the shift register to the latch occurs
when the LE input is high. The data in the latch is retained when
LE is low.
►
CMOS compatible inputs
►
Forward and reverse shifting options
►
Diode to VPP allows efficient power recovery
Typical Application Circuit
VDD
DATA
INPUT
CLK
VPP
HV
OUT
1
Low Voltage
High Voltage
Level
Translators
&
Push-Pull
Output
Buffers
Columns
Micro
Processor
LE
OE
Shift Register
Latches
Output Contr.
Row
Driver
DATA
OUT
HV
OUT
32
Supertex HV5308B
Data Input for cascading the next HV5308B
Display
Panel
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
HV5308B
Ordering Information
Package Options
Device
44-Lead
Quad Cerpac
10.00x10.00mm body
2.35mm height (max)
0.80mm pitch
44-Lead PQFP
.650x.650in body
.190in height (max)
.050in pitch
.653x.653in body
.180in height (max)
.050in pitch
44-Lead PLCC
HV5308B
HV5308DJ-B*
HV5308PG-B-G
HV5308PJ-B-G
-G indicates package is RoHS compliant (‘Green’).
* Hi-Rel process flow available.
Absolute Maximum Ratings
Parameter
Supply voltage, V
DD
Supply voltage, V
PP
Logic input levels
Ground current
1
Continuous total power dissipation
Plastic
Ceramic
Operating temperature range
Plastic
Ceramic
Storage temperature range
2
Pin Configurations
6
1 44
40
Value
-0.5V to +16V
-0.5V to +90V
-0.5V to V
DD
+0.5V
1.5A
1200mW
1500mW
-40
O
C to +85
O
C
-55
O
C to +125
O
C
-65
O
C to +150
O
C
44
1
44-Lead Quad Cerpac (DJ)
(top view)
Absolute Maximum Ratings are those values beyond which damage to the
device may occur. Functional operation under these conditions is not implied.
Continuous operation of the device at the absolute rating level may affect
device reliability. All voltages are referenced to device ground.
Notes:
1. Duty cycle is limited by the total power dissipated in the package.
2. For operation above 25°C ambient derate linearly to maximum
operating temperature at 20mW/°C for plastic and at 15mW/°C for
ceramic.
44-Lead PQFP (PG)
(top view)
1 44
6
40
44-Lead PLCC (PJ)
Product Marking
Top Marking
HV5308DJ-B
LLLLLLLLLL
YYWW
(top view)
Top Marking
Top Marking
Bottom Marking
CCCCCCCCCCC
AAA
YY = Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
*May be part of top marking
YY = Year Sealed
HV5308PG-B
WW = Week Sealed
LLLLLLLLL
L = Lot Number
Bottom Marking
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
CCCCCCCC
YY WW
YY = Year Sealed
WW = Week Sealed
HV5308PJ-B
LLLLLLLLLL
L = Lot Number
A = Assembler ID
Bottom Marking
C = Country of Origin*
= “Green” Packaging
YYWW AAA
CCCCCCCCCCC
AAA
*May be part of top marking
*May be part of top marking
44-Lead Quad Cerpac
(DJ)
44-Lead PQFP
(PG)
Packages may or may not include the following marks: Si or
44-Lead PLCC
(PJ)
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
2
Tel: 408-222-8888
www.supertex.com
HV5308B
Recommended Operating Conditions
(over -40°C to 85°C for plastic and -55°C to 125°C for ceramic)
Sym
V
DD
V
PP
V
IH
V
IL
f
CLK
Parameter
Logic voltage supply
High voltage supply
Input high voltage
Input low voltage
Clock frequency
Min
10.8
8.0
V
DD
- 2.0
0
0
Max
13.2
80
V
DD
2.0
8.0
Units
V
V
V
V
MHz
Power-Up Sequence
Power-up sequence should be the following:
1. Connect ground
2. Apply V
DD
3. Set all inputs (Data, CLK, LE, etc.) to a known state
4. Apply V
PP
5. The V
PP
should not fall below V
DD
or float during operation.
Power-down sequence should be the reverse of the above.
Electrical Characteristics
(V
DC Characteristics
Sym
I
PP
I
DDQ
I
DD
V
OL
(data)
I
IH
I
IL
V
OC
V
OH
V
OL
V
OH
V
OL
Parameter
V
PP
supply current
PP
= 60V, V
DD
= 12V, T
A
= 25°C)
Min
-
-
-
10.5
-
-
-
-
52
-
52
-
Max
0.5
100
15
-
1.0
1.0
-1.0
-1.5
-
8.0
-
8.0
Units
mA
µA
mA
V
V
µA
µA
V
V
V
V
V
Conditions
HV
OUTPUTS
high to low
All inputs = V
DD
or GND
V
DD
= V
DD
max, f
CLK
= 8.0MHz
I
O
= -100µA
I
O
= 100µA
V
IN
= V
DD
V
IN
= 0
I
OL
= -100mA
I
OH
= -20mA, -40 to 85°C
I
OL
= 20mA, -40 to 85°C
I
OH
= -15mA, -55 to 125°C
I
OL
= 15mA, -55 to 125°C
I
DD
supply current (quiescent)
I
DD
supply current (operating)
Shift register output voltage
Current leakage, any input
Current leakage, any input
HV output clamp diode voltage
HV output when sourcing
HV output when sinking
HV output when sourcing
HV output when sinking
V
OH
(data) Shift register output voltage
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
3
Tel: 408-222-8888
www.supertex.com
HV5308B
AC Characteristics
Sym
f
CLK
t
WL
or t
WH
t
SU
t
H
Parameter
Clock frequency
Clock width, HIGH or LOW
Setup time before CLK rises
Hold time after CLK rises
Min
-
62
25
10
-
-
50
50
50
-
-
Max
8.0
-
-
-
110
110
-
-
-
500
500
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
---
---
---
---
C
L
= 15pF
C
L
= 15pF
---
---
---
---
---
t
DLH
(Data) Data output delay after L to H CLK
t
DHL
(Data) Data output delay after H to L CLK
t
DLE
t
WLE
t
SLE
t
ON
t
OFF
LE delay after L to H CLK
Width of LE pulse
LE setup time before L to H CLK
Delay from LE to HV
OUT
, L to H
Delay from LE to HV
OUT
, H to L
Switching Waveforms
DATA
IN
V
IH
50%
t
SU
CLK
50%
t
WL
50%
t
WH
50%
DATA
OUT
t
DLH
50%
t
DHL
50%
LE
t
DLE
HV
OUT
w/ S/R LOW
t
OFF
HV
OUT
10%
t
ON
90%
V
OH
V
OL
t
WLE
90%
10%
t
SLE
V
OH
V
OL
50%
Data Valid
t
H
50%
50%
V
IL
V
OH
V
OL
V
OH
V
OL
V
IH
V
IL
50%
V
IL
V
IH
w/ S/R HIGH
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
4
Tel: 408-222-8888
www.supertex.com
HV5308B
Input and Output Equivalent Circuits
VDD
VDD
VPP
DATA
INPUT
DATA OUT
HV
OUT
GND
Logic Inputs
GND
Logic Data Output
GND
High Voltage Outputs
Functional Block Diagram
VPP
OE
LE
DATA
INPUT
CLK
HV
OUT
1
HV
OUT
2
•
•
•
28 Additional
Outputs
•
•
•
HV
OUT
31
HV
OUT
32
32 bit
Static
Register
32 bit
Latches
DATA
OUT
Function Tables
DATA IN
H
L
X
No
Note:
*
= LOW - to - HIGH transition
H = High
L = Low
X = Don’t Care
CLK*
DATA OUT
H
L
No change
DATA IN
X
X
H
L
LE
X
L
H
H
OE
L
H
H
H
HV OUT
All HV
OUT
= LOW
Previous latched data
H
L
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
5
Tel: 408-222-8888
www.supertex.com
FPGA/CPLD
