HV583
HV583
128-Channel Serial to Parallel Converter
with Push-Pull Outputs
Features
❏
❏
❏
❏
❏
❏
❏
❏
❏
❏
❏
❏
Processed with HVCMOS technology
128 Channels
4 Separate shift registers
5V CMOS logic
Output voltages up to 80V
±30mA output current capability
Low power level shifting
40MHz data shifting
Latched data outputs
Forward and reverse shifting option via DIR pin
Output diode to ground and V
PP
for efficient power recovery
Outputs can be hot switched
General Description
The Supertex HV583 is a 128-channel low voltage serial to high
voltage parallel converter with push-pull outputs. This device has
been designed for use as a display driver. It can also be used in
any application requiring multiple output, high voltage current
sourcing and sinking capability such as plasma displays and
inkjet printers. The device has 4 parallel 32-bit shift registers,
permitting data rates 4X the speed of one. The data are shifted
in during the low to high clock transition. There are also 128
latches and control logic to shift clockwise or counterclockwise.
High at RST input pin clears contents of both: the shift register
and the latch. The outputs can be in a high impedance state via
the output enable logic pin.
Applications
❏
Plasma Displays
❏
Inkjet Printers
Typical Application
Low Voltage
Power Supply
High Voltage
Power Supply
Supertex HV583
DXA
CLK
RST
LE
Micro
Processor
OE
OL
OH
DXB
HV
OUT0
Columns
Low Voltage
High Voltage
Shift Register
Latches
Output Contr.
Level
Translators
&
Push-Pull
Output
Buffers
Row
Driver
HV
OUT127
Display
Panel
DXA for cascading the next HV583
Supertex HV583
1
HV583
Ordering Information
Device
HV583
Recommended
Operating V
PP
Max
80V
Package Options
Die
HV583X
Notes:
Power-up sequence should be the following:
1. Connect ground.
2. Apply V
DD
.
3. Set all inputs (Data, CLK, etc.) to a known state.
4. Apply V
PP
.
-0.5V to +90V
-0.5V to +7.0V
-65mA to +40mA
-65mA to +65mA
-0.5V to V
DD
+0.5V
-25°C to +150°C
-40°C to +150°C
Absolute Maximum Ratings*
V
PP
, High voltage supply
V
DD
, Logic supply voltage
I
OUT
, Output source and sink current
I
DIODE
, Output body diode current
Logic input voltages
Tj, Junction temperature
Storage temperature
Power-down sequence should be the reverse of the above.
*All voltages are referenced to device ground. Absolute maximum ratings are those values
which damage to the device may occur. Functional operation under these conditions is not
implied. Continous operation of the device at the absolute rating level may affect device
reliability.
Operating Conditions
Symbol
V
PP
V
DD
I
OUT
SR
f
CLK
Tj
Parameter
High voltage supply
Low voltage supply
HVout peak output current
V
PP
power supply slew rate
Clock frequency
Min
15
4.5
-30
5.0
Typ
Max
80
5.5
30
8.0
40
25
Operating junction temperature
-25
+125
Units
V
V
mA
V/µs
MHz
MHz
°C
Data read
Cascade connection
Conditions
Cload = 300pF
Electrical Characteristics
DC Characteristics
(Tj = 25°C, V
DD
= 5V, V
PP
= 80V)
Symbol
I
PPQ
I
DDQ
HV
OH
HV
OHD
HV
OL
HV
OLD
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
Parameter
V
PP
quiescent supply current
V
DD
quiescent supply current
High level output voltage
73
10
Output p-channel body diode
Low level output voltage
Output n-channel body diode
Logic input high voltage
Logic input low voltage
Logic input high current
10
Logic input low current
Logic output high
Logic output low
2
-1.0
4.5V
0.5V
30
-1.5
2.0
0
V
DD
0.8
1.0
50
3.0
81.5
6.0
76
V
V
V
V
V
V
µA
µA
µA
V
V
Min
Typ
Max
10
10
Units
µA
µA
I
OUT
= 30mA, V
PP
= 80V
I
OUT
= 10mA, V
PP
= 20V
I
OUT
= -30mA, V
PP
=80V
I
OUT
= -30mA
I
OUT
= +30mA
V
DD
= 4.5V to 5.5V
V
DD
= 4.5V to 5.5V
V
IH
= 5.3V, V
DD
= 5.0V
V
IH
= 5.0V, For DIR only
V
IL
= -0.3V
I
OUT
= 1.0mA
I
OUT
= -1.0mA
Conditions
HV583
AC Electrical Characteristics
(Tj = 25°C, V
DD
= 5V, V
PP
= 80V)
Symbol
twCLK
twLE
tsu1
tsu2
tsu3
th1
th2
tpdHL
tpdLH
tpHL
tpLH
tpHZL
tpLZH
tpHZ
tpLZ
tr
tf
Parameter
Clock pulse width, high and low
LE pulse width, high and low
Setup time, DXAs, DXBs to CLK
Setup time, CLK to LE
Setup time, LE to OL, OH
Hold time, CLK to DXAs, DXBs
Hold time, LE to CLK
CLK to DXAs, DXBs
CLK to DXAs, DXBs
LE, OH, OL to HV
OUT
LE, OH, OL to HV
OUT
OE to HV
OUT
OE to HV
OUT
OE to HV
OUT
OE to HV
OUT
HV
OUT
HV
OUT
Min
10
10
5
10
25
5
10
25
25
150
Typ -20 tpHL+tf Typ +40
150
Typ -20 tpHL+tf Typ +40
300
300
120
120
Typ
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C=15pF
C=15pF
C=50pF
C=80pF
C=50pF
C=80pF
Rl=10K, C=50pF
Rl=10K, C=50pF
C=50pF
C=50pF
Conditions
V
DD
=4.5V to 5.5V,
T25°C to 125°C
V
DD
=4.5V to 5.5V,
Tj=-25°C to 125°C
Shift Register Truth Table
DIR
L or open
L or open
H
H
CLK
L to H
H to L
L to H
H to L
State of Shift Register
Shift
Hold
Shift
Hold
Shift Direction
D
XB
to D
XA
D
XB
to D
XA
D
XA
to D
XB
D
XA
to D
XB
Latch Truth Table
LE
L to H
H to L
Output State of Latch
Latch execution
Hold
HV
OUT
Truth Table
OE
L
H
H
H
H
OL
X
L
H
H
H
OH
X
X
L
H
H
DXA/DXB
X
X
X
L
H
HV
OUT
Z
L
H
L
H
H = Level High
L = Level Low
X = Don’t care. Can be High or Low
Z = High impedance. Open circuit.
3
HV583
Block Diagram
V
DD
V
PP
D
1A
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
HV
OUT
0
D
1B
D
2A
D
2B
Latch
D
3A
D
3B
D
4A
SR
SR
SR
SR
D
124
D
125
D
126
D
127
Q
124
Q
125
Q
126
Q
127
D
4B
CLK
DIR
RST
LE
OH
OL
OE
HV
OUT
127
DGND
PGND
4
HV583
Timing Diagram
CLK
tsu1
DXA/B
(input)
twCLK
twCLK
th1
tsu1
th1
tpLH
DXA/B
(output)
tsu2
LE
tsu3
OL, OH
th2
tpHL
twLE
twLE
OE
OE
50%
50%
LE. OH, OL
tpHZ
tpLZ
HV
OUT
n
90%
10%
tpLZH
tpHZL
90%
10%
10%
tr
tf
tpLH
90%
tpHL
90%
10%
LE, OH, OL
HV
OUT
n
tpHL
HV
OUT
n
tf
tpLH = tpHL + tf
tr
5
