HYB18T2G402BF-3.7,HYB18T2G402BF-3.7 pdf中文资料,HYB18T2G402BF-3.7引脚图,HYB18T2G402BF-3.7电路-Datasheet-电子工程世界

文档预览

November 2007

H Y B 18 T 2G 402B F

H Y B 18 T 2G 802B F

2 - G b i t D u a l D i e D o u b l e - D a t a - R a t e - T w o SD R A M

DDR2 SDRAM

RoHS Compliant Products

Internet Data Sheet

Rev. 1.10

Date: 2007-11-05

Internet Data Sheet

HYB18T2G[40/80]2BF

2-Gbit Dual Die Double-Data-Rate-Two SDRAM

HYB18T2G402BF, HYB18T2G802BF

Revision History: 2007-11, Rev. 1.10

Page

All

Subjects (major changes since last revision)

Adapted internet edition

Corrected Idd1 for DDR2-400B to 150

Added HYB18T2G402BF-2.5 and HYB18T2G802BF-2.5

Previous Revision: 2007-01, Rev. 1.00

Initial Document

We Listen to Your Comments

Any information within this document that you feel is wrong, unclear or missing at all?

Your feedback will help us to continuously improve the quality of this document.

Please send your proposal (including a reference to this document) to:

techdoc@qimonda.com

qag_techdoc_rev411 / 3.31 QAG / 2007-01-22

10192006-0E3U-5BSU

Date: 2007-11-05

Internet Data Sheet

HYB18T2G[40/80]2BF

2-Gbit Dual Die Double-Data-Rate-Two SDRAM

Overview

This chapter gives an overview of the 2-Gbit Dual Die Double-Data-Rate-Two SDRAM product family and describes its main

characteristics.

1.1

Features

The 2-Gbit Dual Die Double-Data-Rate-Two SDRAM offers the following key features:

• Off-Chip-Driver impedance adjustment (OCD) and

• 1.8 V

0.1 V Power Supply

1.8 V

0.1 V (SSTL_18) compatible I/O

On-Die-Termination (ODT) for better signal quality

• Two 1-Gbit dies in a common BGA package

• Auto-Precharge operation for read and write bursts

• DRAM organizations with 4,8 data in/outputs

• Auto-Refresh, Self-Refresh and power saving Power-

• Double Data Rate architecture: two data transfers per

Down modes

clock cycle four internal banks for concurrent operation

• Average Refresh Period 7.8

μs

at a

CASE

lower

• Programmable CAS Latency: 3, 4, 5 and 6

than 85 °C, 3.9

μs

between 85 °C and 95 °C

• Programmable Burst Length: 4 and 8

• High Temperature Self Refresh Mode is supported via

• Differential clock inputs (CK and CK)

EMR(2) A7

• Bi-directional, differential data strobes (DQS and DQS) are

• Programmable self refresh rate via EMR(2) setting

• Programmable partial array refresh via EMR(2) settings

transmitted / received with data. Edge aligned with read

• DCC enabling via EMR(2) setting

data and center-aligned with write data

• Full and reduced Strength Data-Output Drivers

• DLL aligns DQ and DQS transitions with clock

• 1kB page size for ×4 and ×8

• DQS can be disabled for single-ended data strobe

• Packages: PG-TFBGA-71

operation

• RoHS Compliant Products

• Commands entered on each positive clock edge, data and

data mask are referenced to both edges of DQS

• All Speed grades faster than DDR2–400 comply with

• Data masks (DM) for write data

DDR2–400 timing specifications when run at a clock rate

• Posted CAS by programmable additive latency for better

of 200 MHz

command and data bus efficiency

1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined

in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,

lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.

Rev. 1.10, 2007-11

10192006-0E3U-5BSU

Date: 2007-11-05

Internet Data Sheet

HYB18T2G[40/80]2BF

2-Gbit Dual Die Double-Data-Rate-Two SDRAM

TABLE 1

Performance Table

QAG Speed Code

DRAM Speed Grade

CAS-RCD-RP latencies

Max. Clock Frequency CL3

CL4

CL5

CL6

Min. RAS-CAS-Delay

Min. Row Precharge Time

Min. Row Active Time

Min. Row Cycle Time

DDR2

–2.5

–800E

6–6–6

–3S

–667D

5–5–5

200

266

333

–

–3.7

–533C

4–4–4

200

266

–

–5

–400B

3–3–3

200

–

Unit

MHz

CK3

CK4

CK5

CK6

RCD

RAS

200

266

333

400

1.2

Description

CK falling). All I/Os are synchronized with a single ended

DQS or differential DQS-DQS pair in a source synchronous

fashion.

A 17 bit address bus for

×4

and

×8

organised components is

used to convey row, column and bank address information in

a RAS-CAS multiplexing style.

The DDR2 device operates with a 1.8 V

0.1 V power

supply. An Auto-Refresh and Self-Refresh mode is provided

along with various power-saving power-down modes.

Since dual-die components share the same DQ bus, each of

the two 1-Gbit dies can be individually selected by its own CS,

CKE and ODT signal. All other signals are common for both

dies.

The functionality described and the timing specifications

included in this data sheet are for the DLL Enabled mode of

operation.

The DDR2 SDRAM is available in TFBGA package.

The 2-Gbit DDR2 DRAM consists of two 1-Gbit Double Data-

Rate-Two dies in one package. Each 1-Gbit device is

organized as 32 Mbit

×4

I/O

×8

banks or 16 Mbit

×8

I/O

×8

banks chip.

These synchronous devices achieve high speed transfer

rates starting at 400 Mb/sec/pin for general applications. See

Table 1

for performance figures.

The device is designed to comply with all DDR2 DRAM key

features:

1. Posted CAS with additive latency.

2. Write latency = read latency - 1.

3. Normal and weak strength data-output driver.

4. Off-Chip Driver (OCD) impedance adjustment.

5. On-Die Termination (ODT) function.

All of the control and address inputs are synchronized with a

pair of externally supplied differential clocks. Inputs are

latched at the cross point of differential clocks (CK rising and

Rev. 1.10, 2007-11

10192006-0E3U-5BSU

Date: 2007-11-05

Internet Data Sheet

HYB18T2G[40/80]2BF

2-Gbit Dual Die Double-Data-Rate-Two SDRAM

TABLE 2

Ordering Information for RoHS Compliant Products

Product Type

HYB18T2G402BF-2.5

HYB18T2G802BF-2.5

HYB18T2G402BF-3S

HYB18T2G802BF-3S

HYB18T2G402BF-3.7

HYB18T2G802BF-3.7

HYB18T2G402BF-5

HYB18T2G802BF-5

Org Speed

DDR2-800E

DDR2-667D

DDR2-533C

DDR2-400B

CAS-RCD-RP

Latencies

1)2)3)

6-6-6

5-5-5

4-4-4

3-3-3

Clock (MHz) Package

400

333

266

200

PG-TFBGA-71

Note

CAS: Column Address Strobe

RCD: Row Column Delay

RP: Row Precharge

RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined

in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,

lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.

Note: For product nomenclature see

Chapter 9

of this data sheet

Rev. 1.10, 2007-11

10192006-0E3U-5BSU

Date: 2007-11-05

参数对比

与HYB18T2G402BF-3.7相近的元器件有：HYB18T2G402BF-2.5、HYB18T2G402BF-3S、HYB18T2G402BF-5、HYB18T2G802BF-3S、HYB18T2G802BF-5、HYB18T2G802BF-3.7、HYB18T2G802BF-2.5。描述及对比如下：

型号	HYB18T2G402BF-3.7	HYB18T2G402BF-2.5	HYB18T2G402BF-3S	HYB18T2G402BF-5	HYB18T2G802BF-3S	HYB18T2G802BF-5	HYB18T2G802BF-3.7	HYB18T2G802BF-2.5
描述	DDR DRAM, 512MX4, 0.8ns, CMOS, PBGA71, GREEN, PLASTIC, TFBGA-71	DDR DRAM, 512MX4, 0.7ns, CMOS, PBGA71, GREEN, PLASTIC, TFBGA-71	DDR DRAM, 512MX4, 0.75ns, CMOS, PBGA71, GREEN, PLASTIC, TFBGA-71	DDR DRAM, 512MX4, 0.9ns, CMOS, PBGA71, GREEN, PLASTIC, TFBGA-71	DDR DRAM, 256MX8, 0.75ns, CMOS, PBGA71, GREEN, PLASTIC, TFBGA-71	DDR DRAM, 256MX8, 0.9ns, CMOS, PBGA71, GREEN, PLASTIC, TFBGA-71	DDR DRAM, 256MX8, 0.8ns, CMOS, PBGA71, GREEN, PLASTIC, TFBGA-71	DDR DRAM, 256MX8, 0.7ns, CMOS, PBGA71, GREEN, PLASTIC, TFBGA-71
是否Rohs认证	符合	符合	符合	符合	符合	符合	符合	符合
零件包装代码	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA
包装说明	LFBGA, BGA71,9X19,32	LFBGA, BGA71,9X19,32	LFBGA, BGA71,9X19,32	LFBGA, BGA71,9X19,32	LFBGA, BGA71,9X19,32	LFBGA, BGA71,9X19,32	LFBGA, BGA71,9X19,32	LFBGA, BGA71,9X19,32
针数	71	71	71	71	71	71	71	71
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown
ECCN代码	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
访问模式	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST
最长访问时间	0.8 ns	0.7 ns	0.75 ns	0.9 ns	0.75 ns	0.9 ns	0.8 ns	0.7 ns
其他特性	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	266 MHz	400 MHz	333 MHz	200 MHz	333 MHz	200 MHz	266 MHz	400 MHz
I/O 类型	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
交错的突发长度	4,8	4,8	4,8	4,8	4,8	4,8	4,8	4,8
JESD-30 代码	R-PBGA-B71	R-PBGA-B71	R-PBGA-B71	R-PBGA-B71	R-PBGA-B71	R-PBGA-B71	R-PBGA-B71	R-PBGA-B71
长度	17 mm	17 mm	17 mm	17 mm	17 mm	17 mm	17 mm	17 mm
内存密度	2147483648 bit	2147483648 bit	2147483648 bit	2147483648 bit	2147483648 bit	2147483648 bit	2147483648 bit	2147483648 bit
内存集成电路类型	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM
内存宽度	4	4	4	4	8	8	8	8
功能数量	1	1	1	1	1	1	1	1
端口数量	1	1	1	1	1	1	1	1
端子数量	71	71	71	71	71	71	71	71
字数	536870912 words	536870912 words	536870912 words	536870912 words	268435456 words	268435456 words	268435456 words	268435456 words
字数代码	512000000	512000000	512000000	512000000	256000000	256000000	256000000	256000000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	95 °C	95 °C	95 °C	95 °C	95 °C	95 °C	95 °C	95 °C
组织	512MX4	512MX4	512MX4	512MX4	256MX8	256MX8	256MX8	256MX8
输出特性	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	LFBGA	LFBGA	LFBGA	LFBGA	LFBGA	LFBGA	LFBGA	LFBGA
封装等效代码	BGA71,9X19,32	BGA71,9X19,32	BGA71,9X19,32	BGA71,9X19,32	BGA71,9X19,32	BGA71,9X19,32	BGA71,9X19,32	BGA71,9X19,32
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH
电源	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
刷新周期	8192	8192	8192	8192	8192	8192	8192	8192
座面最大高度	1.3 mm	1.3 mm	1.3 mm	1.3 mm	1.3 mm	1.3 mm	1.3 mm	1.3 mm
自我刷新	YES	YES	YES	YES	YES	YES	YES	YES
连续突发长度	4,8	4,8	4,8	4,8	4,8	4,8	4,8	4,8
最大待机电流	0.024 A	0.024 A	0.024 A	0.024 A	0.024 A	0.024 A	0.024 A	0.024 A
最大压摆率	0.28 mA	0.34 mA	0.295 mA	0.265 mA	0.295 mA	0.265 mA	0.28 mA	0.34 mA
最大供电电压 (Vsup)	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V
最小供电电压 (Vsup)	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V
标称供电电压 (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
表面贴装	YES	YES	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER
端子形式	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL
端子节距	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm
端子位置	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
宽度	10 mm	10 mm	10 mm	10 mm	10 mm	10 mm	10 mm	10 mm
Base Number Matches	-	1	1	1	1	1	-	-