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HYB25DC256160CF-6

DDR DRAM, 16MX16, 0.7ns, CMOS, PBGA60, 8 X 12 MM, GREEN, PLASTIC, TFBGA-60

器件类别：存储    存储   

厂商名称：QIMONDA

器件标准：

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参数 预览 参数对比
器件参数
参数名称
属性值
是否Rohs认证
符合
零件包装代码
BGA
包装说明
TBGA, BGA60,9X12,40/32
针数
60
Reach Compliance Code
unknown
ECCN代码
EAR99
访问模式
FOUR BANK PAGE BURST
最长访问时间
0.7 ns
其他特性
AUTO/SELF REFRESH
最大时钟频率 (fCLK)
166 MHz
I/O 类型
COMMON
交错的突发长度
2,4,8
JESD-30 代码
R-PBGA-B60
长度
12 mm
内存密度
268435456 bit
内存集成电路类型
DDR DRAM
内存宽度
16
湿度敏感等级
3
功能数量
1
端口数量
1
端子数量
60
字数
16777216 words
字数代码
16000000
工作模式
SYNCHRONOUS
最高工作温度
70 °C
最低工作温度
组织
16MX16
输出特性
3-STATE
封装主体材料
PLASTIC/EPOXY
封装代码
TBGA
封装等效代码
BGA60,9X12,40/32
封装形状
RECTANGULAR
封装形式
GRID ARRAY, THIN PROFILE
峰值回流温度（摄氏度）
260
电源
2.6 V
认证状态
Not Qualified
刷新周期
4096
座面最大高度
1.2 mm
自我刷新
YES
连续突发长度
2,4,8
最大待机电流
0.005 A
最大压摆率
0.215 mA
最大供电电压 (Vsup)
2.7 V
最小供电电压 (Vsup)
2.3 V
标称供电电压 (Vsup)
2.5 V
表面贴装
YES
技术
CMOS
温度等级
COMMERCIAL
端子形式
BALL
端子节距
1 mm
端子位置
BOTTOM
处于峰值回流温度下的最长时间
40
宽度
8 mm
Base Number Matches
1
文档预览
November 2007
HYB25DC256160C[E/F/T]
HYB25DC256800C[E/F]
256 Mbit Double-Data-Rate SDRAM
DDR SDRAM
RoHS Compliant
Internet Data Sheet
Rev. 1.41
Internet Data Sheet
HYB25DC256[16/80]0C[E/F/T]
256 Mbit Double-Data-Rate SDRAM
HYB25DC256160C[E/F/T], HYB25DC256800C[E/F]
Revision History: 2007-11, Rev. 1.41
Page
All
All
17
All
Subjects (major changes since last revision)
Adapted Internet Version
Editorial changes
Corrected mode register definition in chapter 3.2
Qimonda template update
Editorial changes
Previous Revision: 2007-04, Rev. 1.40
Previous Revision: 2006-09, Rev. 1.32
Previous Revision: 2006-07, Rev. 1.31
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
techdoc@qimonda.com
qag_techdoc_rev400 / 3.2 QAG / 2006-08-01
03062006-W5X1-KV12
2
Internet Data Sheet
HYB25DC256[16/80]0C[E/F/T]
256 Mbit Double-Data-Rate SDRAM
1
1.1
•
•
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•
•
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•
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Overview
Features
This chapter lists all main features of the product family HYB25D256[16/40/80]0C[E/C/F/T](L) and the ordering information.
Double data rate architecture: two data transfers per clock cycle
Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
DQS is edge-aligned with data for reads and is center-aligned with data for writes
Differential clock inputs (CK and CK)
Four internal banks for concurrent operation
Data mask (DM) for write data
DLL aligns DQ and DQS transitions with CK transitions
Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
Burst Lengths: 2, 4, or 8
CAS Latency: 1.5 (DDR200 only), 2, 2.5, 3
Auto Precharge option for each burst access
Auto Refresh and Self Refresh Modes
RAS-lockout supported
t
RAP
=
t
RCD
7.8
μs
Maximum Average Periodic Refresh Interval
2.5 V (SSTL_2 compatible) I/O
V
DDQ
= 2.6 V
±
0.1 V
V
DD
= 2.6 V
±
0.1 V
PG-TFBGA-60 package with 3 depopulated rows (8
×
12 mm
2
)
P(G)-TSOPII-66 package
Lead- and halogene-free = green product
TABLE 1
Performance
Part Number Speed Code
Speed Grade
Max. Clock Frequency
Component
@CL3
@CL2.5
@CL2
–5
DDR400B
–6
DDR333B
166
166
133
Unit
—
MHz
MHz
MHz
f
CK3
f
CK2.5
f
CK2
200
166
133
Rev. 1.41, 2007-11
03062006-W5X1-KV12
3
Internet Data Sheet
HYB25DC256[16/80]0C[E/F/T]
256 Mbit Double-Data-Rate SDRAM
1.1.1
Description
The 256 Mbit Double-Data-Rate SDRAM is a high-speed CMOS, dynamic random-access memory containing
268,435,456 bits. It is internally configured as a quad-bank DRAM.
The 256 Mbit Double-Data-Rate SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double
data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock
cycle at the I/O pins. A single read or write access for the 256 Mbit Double-Data-Rate SDRAM effectively consists of a single
2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle
data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a
strobe transmitted by the DDR SDRAM during Reads and by the memory controller during Writes. DQS is edge-aligned with
data for Reads and center-aligned with data for Writes.
The 256 Mbit Double-Data-Rate SDRAM operates from a differential clock (CK and CK; the crossing of CK going HIGH and
CK going LOW is referred to as the positive edge of CK). Commands (address and control signals) are registered at every
positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as
well as to both edges of CK.Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration
of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the
Active command are used to select the bank and row to be accessed. The address bits registered coincident with the Read or
Write command are used to select the bank and the starting column location for the burst access.
The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4 or 8 locations. An Auto Precharge function
may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard SDRAMs,
the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high effective
bandwidth by hiding row precharge and activation time.
An auto refresh mode is provided along with a power-saving power-down mode. All inputs are compatible with the JEDEC
Standard for SSTL_2. All outputs are SSTL_2, Class II compatible.
Note: The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of
operation.
TABLE 2
Ordering Information for Lead Containing Products
Product Type
1)
HYB25DC256160CT–6
Org.
×16
CAS-RCD-RP
Latencies
2.5-3-3
Clock
(MHz)
166
CAS-RCD-RP
Latencies
2-3-3
Clock
(MHz)
133
Speed
DDR333B
Package
P(G)-TSOPII-66
Rev. 1.41, 2007-11
03062006-W5X1-KV12
4
Internet Data Sheet
HYB25DC256[16/80]0C[E/F/T]
256 Mbit Double-Data-Rate SDRAM
TABLE 3
Ordering Informationfor Lead free (RoHS
1)
Compliant) Products
Product Type
1)
HYB25DC256800CE–5
HYB25DC256160CE–5
HYB25DC256160CE–6
HYB25DC256800CF–5
HYB25DC256160CF–5
HYB25DC256160CF–6
HYB25DC256800CE-6
×8
×8
×16
2.5-3-3
166
2-3-3
133
DDR333B
PG-TSOPII-66
Org.
×8
×16
2.5-3-3
3-3-3
166
200
2-3-3
2-3-3
133
166
DDR333B
DDR400A
PG-TFBGA-60
CAS-RCD-RP
Latencies
3-3-3
Clock
(MHz)
200
CAS-RCD-RP
Latencies
2.5-3-3
Clock
(MHz)
166
Speed
DDR400B
Package
P(G)-TSOPII-66
1) HYB: designator for memory components
25D: DDR SDRAMs at
V
DDQ
= 2.5 V
256: 256-Mbit density
400/800/160: Product variations
×4, ×8
and
×16
C: Die revision C
L: low power (available on request)
T/E/F/C: Package type TSOP(contains Lead), TSOP(Lead & Halone free), FBGA(Lead & Halone free) and FBGA (contains Lead)
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.41, 2007-11
03062006-W5X1-KV12
5
查看更多>
参数对比
与HYB25DC256160CF-6相近的元器件有：HYB25DC256160CE-6、HYB25DC256800CF-5、HYB25DC256160CE-5、HYB25DC256160CT-6、HYB25DC256800CE-6、HYB25DC256160CF-5、HYB25DC256800CE-5。描述及对比如下：
型号 HYB25DC256160CF-6 HYB25DC256160CE-6 HYB25DC256800CF-5 HYB25DC256160CE-5 HYB25DC256160CT-6 HYB25DC256800CE-6 HYB25DC256160CF-5 HYB25DC256800CE-5
描述 DDR DRAM, 16MX16, 0.7ns, CMOS, PBGA60, 8 X 12 MM, GREEN, PLASTIC, TFBGA-60 DDR DRAM, 16MX16, 0.7ns, CMOS, PDSO66, GREEN, PLASTIC, TSOP2-66 DDR DRAM, 32MX8, 0.5ns, CMOS, PBGA60, 8 X 12 MM, GREEN, PLASTIC, TFBGA-60 DDR DRAM, 16MX16, 0.5ns, CMOS, PDSO66, GREEN, PLASTIC, TSOP2-66 DDR DRAM, 16MX16, 0.7ns, CMOS, PDSO66, PLASTIC, TSOP2-66 DDR DRAM, 32MX8, 0.7ns, CMOS, PDSO66, GREEN, PLASTIC, TSOP2-66 DDR DRAM, 16MX16, 0.5ns, CMOS, PBGA60, 8 X 12 MM, GREEN, PLASTIC, TFBGA-60 DDR DRAM, 32MX8, 0.5ns, CMOS, PDSO66, GREEN, PLASTIC, TSOP2-66
是否Rohs认证 符合 符合 符合 符合 不符合 符合 符合 符合
零件包装代码 BGA TSOP2 BGA TSOP2 TSOP2 TSOP2 BGA TSOP2
包装说明 TBGA, BGA60,9X12,40/32 TSSOP, TSSOP66,.46 TBGA, BGA60,9X12,40/32 TSSOP, TSSOP66,.46 TSSOP, TSSOP66,.46 TSSOP, TSSOP66,.46 TBGA, BGA60,9X12,40/32 TSSOP, TSSOP66,.46
针数 60 66 60 66 66 66 60 66
Reach Compliance Code unknown unknown unknown unknown unknown unknown unknown unknow
ECCN代码 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99
访问模式 FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST
最长访问时间 0.7 ns 0.7 ns 0.5 ns 0.5 ns 0.7 ns 0.7 ns 0.5 ns 0.5 ns
其他特性 AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH
最大时钟频率 (fCLK) 166 MHz 166 MHz 200 MHz 200 MHz 166 MHz 166 MHz 200 MHz 200 MHz
I/O 类型 COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON
交错的突发长度 2,4,8 2,4,8 2,4,8 2,4,8 2,4,8 2,4,8 2,4,8 2,4,8
JESD-30 代码 R-PBGA-B60 R-PDSO-G66 R-PBGA-B60 R-PDSO-G66 R-PDSO-G66 R-PDSO-G66 R-PBGA-B60 R-PDSO-G66
长度 12 mm 22.22 mm 12 mm 22.22 mm 22.22 mm 22.22 mm 12 mm 22.22 mm
内存密度 268435456 bit 268435456 bit 268435456 bit 268435456 bit 268435456 bit 268435456 bit 268435456 bit 268435456 bi
内存集成电路类型 DDR DRAM DDR DRAM DDR DRAM DDR DRAM DDR DRAM DDR DRAM DDR DRAM DDR DRAM
内存宽度 16 16 8 16 16 8 16 8
功能数量 1 1 1 1 1 1 1 1
端口数量 1 1 1 1 1 1 1 1
端子数量 60 66 60 66 66 66 60 66
字数 16777216 words 16777216 words 33554432 words 16777216 words 16777216 words 33554432 words 16777216 words 33554432 words
字数代码 16000000 16000000 32000000 16000000 16000000 32000000 16000000 32000000
工作模式 SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
最高工作温度 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C
组织 16MX16 16MX16 32MX8 16MX16 16MX16 32MX8 16MX16 32MX8
输出特性 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 TBGA TSSOP TBGA TSSOP TSSOP TSSOP TBGA TSSOP
封装等效代码 BGA60,9X12,40/32 TSSOP66,.46 BGA60,9X12,40/32 TSSOP66,.46 TSSOP66,.46 TSSOP66,.46 BGA60,9X12,40/32 TSSOP66,.46
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 GRID ARRAY, THIN PROFILE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH GRID ARRAY, THIN PROFILE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH GRID ARRAY, THIN PROFILE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源 2.6 V 2.6 V 2.6 V 2.6 V 2.6 V 2.5 V 2.6 V 2.6 V
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
刷新周期 4096 4096 8192 4096 4096 8192 4096 8192
座面最大高度 1.2 mm 1.2 mm 1.2 mm 1.2 mm 1.2 mm 1.2 mm 1.2 mm 1.2 mm
自我刷新 YES YES YES YES YES YES YES YES
连续突发长度 2,4,8 2,4,8 2,4,8 2,4,8 2,4,8 2,4,8 2,4,8 2,4,8
最大待机电流 0.005 A 0.005 A 0.005 A 0.005 A 0.005 A 0.005 A 0.005 A 0.005 A
最大压摆率 0.215 mA 0.215 mA 0.25 mA 0.25 mA 0.215 mA 0.215 mA 0.25 mA 0.25 mA
最大供电电压 (Vsup) 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V
最小供电电压 (Vsup) 2.3 V 2.3 V 2.5 V 2.5 V 2.3 V 2.3 V 2.5 V 2.5 V
标称供电电压 (Vsup) 2.5 V 2.5 V 2.6 V 2.6 V 2.5 V 2.5 V 2.6 V 2.6 V
表面贴装 YES YES YES YES YES YES YES YES
技术 CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
温度等级 COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
端子形式 BALL GULL WING BALL GULL WING GULL WING GULL WING BALL GULL WING
端子节距 1 mm 0.65 mm 1 mm 0.65 mm 0.65 mm 0.65 mm 1 mm 0.65 mm
端子位置 BOTTOM DUAL BOTTOM DUAL DUAL DUAL BOTTOM DUAL
宽度 8 mm 10.16 mm 8 mm 10.16 mm 10.16 mm 10.16 mm 8 mm 10.16 mm
湿度敏感等级 3 1 3 1 - - 3 1
峰值回流温度（摄氏度） 260 260 260 260 - - 260 260
处于峰值回流温度下的最长时间 40 40 40 40 - - 40 40
厂商名称 - QIMONDA QIMONDA QIMONDA QIMONDA QIMONDA QIMONDA QIMONDA
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器件捷径:
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ
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