Integrated
Circuit
Systems, Inc.
ICS2494
ICS2494A
Dual Video/Memory Clock Generator
Features
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World standard
ICS2494A
has been reconfigured
to allow 8 memory frequencies.
Mask-programmable frequencies
Pre-programmed versions for Industry Standard
VGA chips
Glitch-free frequency transitions
Provision for external frequency input
Internal clock remains locked when the external
frequency input is selected
Low power CMOS device technology
Small footprint - 20-pin DIP or SOIC
New Features
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Buffered XTAL Out
Integral loop filter components
Fast acquisition of selected frequencies, strobed or non-
strobed
Guaranteed performance up to 135 MHz
Excellent power supply rejection
Advanced PLL for low phase-jitter
Frequency change detection circuitry which enhances new
frequency acquisition and eliminates problems caused by
programs that rewrite frequency information.
Improved pinout - easier board layout.
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Applications
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VGA-Super VGA-XGA video adapters
Workstations
8514A-TMS34010-TMS34020
Motherboard
Pin Configuration
Description
The Dot Clock Generator is an integrated circuit dual phase-
locked loop frequency synthesizer capable of generating six-
teen video dot clock frequencies and eight memory clock
frequencies for use with high performance video display sys-
tems. Utilizing CMOS technology to implement all linear,
digital and memory functions, the
ICS2494/94A
provides a
low-power, small-footprint, low-cost solution to the generation
of video dot clocks. Outputs are compatible with XGA, VGA,
EGA, MCGA, CGA, MDA, as well as the higher frequencies
needed for advanced applications in desktop publishing and
workstation graphics. Provision is made via a single-level
custom mask to implement customer-specific frequency sets.
Phase-locked loop circuitry permits rapid glitch-free transi-
tions between clock frequencies.
XTAL1
XTAL
EXTFREQ
FS0
FS1
STROBE
FS2
FS3
MS0
MS0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DVDD
VCLK
XTALOUT
VSS
VSS
AVDD
VSS
DVDD
MCLK
MS1
20-Pin DIP or SOIC
Notes:
1. In applications where the external frequency input is not specified,
EXTFREQ must be tied to Vss.
2. ICS2494/94AM(SOIC) pinout is identical to ICS2494/94AN(DIP).
2494/94ARevA090694
ICS2494
ICS2494A
Circuit and Application Options
The
ICS2494/94A
will typically derive its frequency reference
from a series-resonant crystal connected between pins 1 and 2.
Where a high quality reference signal is available, such as in
an application where the graphics subsystem is resident on the
motherboard, this reference may directly replace the crystal.
This signal should be coupled to pin 1. If the reference signal
amplitude is less than 3.5 volts, a .047 microfarad capacitor
should be used to couple the reference signal into
XTAL1.
Pin
2 must be left open.
Power Supply Conditioning
The
ICS2494/94A
is a member of the second generation of dot
clock products. By incorporating the loop filter on chip and
upgrading the VCO, the ease of application has been substan-
tially improved over earlier products. If a stable and noise-free
power supply is available, no external components are re-
quired. However, in most applications it is judicious to decou-
ple the power supply as shown in Figures 1 or 2. Figure 1 is the
normal configuration for 5 volt only applications. Which of the
two provides superior performance depends on the noise con-
tent of the power supplies. In general, the configuration of
Figure 1 is satisfactory. Figure 2 is the more conventional if a
12 volt analog supply is available, although the improved
performance comes at a cost of an extra component. The cost
of the discretes used in Figure 2, however, are less than the cost
of Figure 1’s discrete components.
The number and differentiation of the analog and digital supply
pins are intended for maximum performance products. In most
applications, all VDDs may be tied together. The function of
the multiple pins is to allow the user to realize the maximum
performance from the silicon with a minimum degradation due
to the package and PCB. At the frequencies of interest, the
effects of the inductance of the bond wires and package lead
frame are non-trivial. By using the multiple pins, ICS mini-
mized the effect of packaging and minimized the interaction of
the digital and analog supply currents.
Figure 1
ICS2494A
2
ICS2494
ICS2494A
Applications
Layout Considerations
Utilizing the
ICS2494/94A
in video graphics adapter cards or
on PS2 motherboards is simple but does require precautions in
board layout if satisfactory jitter-free performance is to be
realized. Care should be exercised in ensuring that components
not related to the
ICS2494/94A
do not share its ground. In
applications utilizing a multi-layer board, VSS should be di-
rectly connected to the ground plane. Multiple pins are utilized
for all analog and digital VSS and VDD connections to permit
extended frequency VCLK operation to 135 MHz. However,
in all cases, all VSS and VDD pins should be connected.
The
ICS2494/94A
is not sensitive to the duty cycle of the bus
clock; however, the quality of this signal varies considerably
with different motherboard designs. As the quality of this
signal is typically outside of the control of the graphics adapter
card manufacturer, it is suggested that this signal be buffered
on the graphics adapter board.
XTAL2 (2)
must be left open in
this configuration.
Buffered XTALOUT
In motherboard applications it may be desirable to have the
ICS2494/94A
provide the bus clock for the rest of the system.
This eliminates the need for an additional 14.31818 MHz
crystal oscillator in the system, saving money as well as board
space. To do this, the
XTALOUT (18)
output should be buff-
ered with a CMOS driver.
Figure 2
Output Circuit Considerations
As the dot clock is usually the highest frequency present in a
video graphics system, consideration should be given to EMI.
To minimize problems with meeting FCC EMI requirements,
the trace which connects
VCLK (19) or MCLK (12)
and other
components in the system should be kept as short as possible.
The
ICS2494/94A
outputs have been designed to minimize
overshoot. In addition it may be helpful to place a ferrite bead
in these signal paths to limit the propagation of high order
harmonics of this signal. A suitable device would be a Ferrox-
cube 56-590-65/4B or equivalent. This device should be placed
physically close to the
ICS2494/94A.
A 33 to 47 Ohm series
resistor, sometimes called source termination, in this path may
be necessary to reduce ringing and reflection of the signal and
may reduce phase-jitter as well as EMI.
ICS2494A
Digital Inputs
Frequency Reference
The internal reference oscillator contains all of the passive
components required. An appropriate series-resonant crystal
should be connected between
XTAL1 (1)
and
XTAL2 (2).
In
IBM-compatible applications this will typically be a 14.31818
MHz crystal, but fundamental mode crystals between 10 MHz
and 25 MHz have been tested. Maintain short lead lengths
between the crystal and the
ICS2494/94A.
In some applica-
tions, it may be desirable to utilize the bus clock. If the signal
amplitude is equal to or greater than 3.5 volts, it may be
connected directly to
XTAL1 (1).
If the signal amplitude is less
than 3.5 volts, connect the clock through a .047 microfarad
capacitor to
XTAL1 (1),
and keep the lead length of the
capacitor to
XTAL1 (1)
to a minimum to reduce noise suscep-
tibility. This input is internally biased at VDD/2. Since TTL
compatible clocks typically exhibit a VOH of 3.5V, capaci-
tively coupling the input restores noise immunity.
FS0 (4), FS1 (5), FS2 (7),
and
FS3 (8)
are the TTL compatible
frequency select inputs for the binary code corresponding to
the frequency desired.
STROBE (6),
when high, allows new
data into the frequency select latches; and when low, prevents
address changes per Figure 3. The internal power-on-clear
signal will force an initial frequency code corresponding to an
all zeros input state.
MS0 (9), MS1 (11)
and
MS2 (3)
are the
corresponding memory select inputs and are not strobed.
3
ICS2494
ICS2494A
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . V
DD
. . . . . . . . . . . . -0.5V to +7V
Input Voltage. . . . . . . . . . . . . . . . . . V
IN
. . . . . . . . . . . . . -0.5V to V
DD
+0.5V
Output Voltage . . . . . . . . . . . . . . . . V
OUT
. . . . . . . . . . . -0.5V to VDD+0.5V
Clamp Diode Current . . . . . . . . . . . V
IK
& I
OK
. . . . . . .
±30mA
Output Current per Pin . . . . . . . . . . I
OUT
. . . . . . . . . . . .
±50mA
Operating Temperature . . . . . . . . . . T
o
. . . . . . . . . . . . . . 0
°C
to 70
°C
Storage Temperature . . . . . . . . . . . . T
S
. . . . . . . . . . . . . . -85
°C
to +150
°C
Power Dissipation. . . . . . . . . . . . . . P
D
. . . . . . . . . . . . . . 500mW
Values beyond these ratings may damage the device. This device contains circuitry to protect the inputs and outputs against
damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applications
of any voltage higher than the maximum rated voltages. For proper operation it is recommended that V
IN
and V
OUT
be constrained
to >= V
SS
and <=V
DD.
DC Characteristics (0
o
C to 70
o
C)
SYMBOL
V
DD
V
IL
V
IH
I
IH
V
OL
V
OH
I
DD
R
UP *
C
in
C
out
PARAMETER
Operating Voltage Range
Input Low Voltage
Input High Voltage
Input Leakage Current
Output Low Voltage
Output High Voltage
Supply Current
Internal Pull-up Resistors
Input Pin Capacitance
Output Pin Capacitance
MIN
4.0
V
ss
2.0
-
-
2.4
-
50
-
-
MAX
5.5
0.8
V
dd
10
0.4
-
35
200
8
12
UNITS
V
V
V
uA
V
V
mA
K Ohm
pF
pF
CONDITIONS
V
dd
= 5V
V
dd
= 5V
V
in
= V
cc
I
ol
= 4.0 mA
I
oh
= 4.0 mA
V
dd
= 5V, VCLK = 80 MHz
V
dd
= 5V, V
in
= 0V
F
c
= 1 MHz
F
c
= 1 MHz
* The following inputs have pull-ups: FS0-3, MS0-1, STROBE.
Frequency Pattern Availability
ICS offers the largest variety of standard frequency patterns in
the industry, supporting all popular VGA controller devices.
The attached listing provides the selection as of this publication
date. Contact your local ICS sales office for latest frequency
pattern availability.
ICS2494
ICS2494A
AC Timing Characteristics
The following notes apply to all parameters presented in this section:
1. Xtal Frequency = 14.31818 MHz
2. T
C
= 1/ F
C
3. All units are in nanoseconds (ns).
4. Rise and fall time is between 0.8 and 2.0 VDC.
5. Output pin loading = 25pF
6. Duty cycle is measured at 1.4V.
7. Supply Voltage Range = 4.0 to 5.5 Volts
8. Temperature Range = 0
°
C to 70
°
C
SYMBOL
Tpw
Tsu
Thd
Tr
Tf
-
-
-
PARAMETER
Strobe Pulse Width
Setup Time Data to Strobe
Hold Time Data to Strobe
Rise Time
Fall Time
Frequency Error
Maximum Frequency
Propagation Delay for
Pass Through Frequency
MIN
STROBE TIMING
20
10
10
MCLK AND VCLK TIMINGS
-
-
-
MAX
-
-
-
3
3
0.5
135
15
Duty Cycle 40% min. to
60% max.
%
MHz
ns
NOTES
Figure 3
