PRELIMINARY INFORMATION
ICS291
Triple PLL Field Prog. Spread Spectrum Clock Synthesizer
Description
The ICS291 field programmable spread spectrum clock
synthesizer generates up to six high-quality,
high-frequency clock outputs including multiple
reference clocks from a low-frequency crystal input. It
is designed to replace crystals, crystal oscillators and
stand alone spread spectrum devices in most
electronic systems.
Using ICS’ VersaClock
TM
software to configure PLLs
and outputs, the ICS291 contains a One-Time
Programmable (OTP) ROM for field programmability.
Programming features include input/output
frequencies, spread spectrum amount, eight selectable
configuration registers and up to two sets of three
low-skew outputs.
Each of the two output groups are powered by a
separate VDDO voltage. VDDO may vary from 1.8 V to
VDD.
Using Phase-Locked Loop (PLL) techniques, the
device runs from a standard fundamental mode,
inexpensive crystal, or clock. It can replace multiple
crystals and oscillators, saving board space and cost.
The ICS291 is also available in factory programmed
custom versions for high-volume applications.
Features
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Packaged as 20-pin TSSOP
Eight addressable registers
Replaces multiple crystals and oscillators
Output frequencies up to 200 MHz at 3.3 V
Configurable Spread Spectrum Modulation
Input crystal frequency of 5 to 27 MHz
Clock input frequency of 3 to 166 MHz
Up to six reference outputs
Separate 1.8 to 3.3 V VDDO output level controls for
each bank of 3 outputs
Up to two sets of three low-skew outputs
Operating voltages of 3.3 V
Controllable output drive levels
Advanced, low-power CMOS process
Available in Pb (lead) free packaging
Block Diagram
VDD
PLL1 with
Spread
Spectrum
Divide
Logic
and
Output
Enable
Control
3
VDDO1
S2:S0
3
OTP
ROM
with PLL
Values
CLK1
CLK2
CLK3
PLL2
CLK4
CLK5
CLK6
PLL3
X1/ICLK
Crystal or
Clock Input
Crystal
Oscillator
X2
External capacitors
are required with a crystal input.
3
GND
PDTS
VDDO2
MDS 291 C
Integrated Circuit Systems, Inc.
●
1
525 Race Street, San Jose, CA 95126
●
Revision 062205
tel (408) 297-1201
●
www.icst.com
PRELIMINARY INFORMATION
ICS291
Triple PLL Field Prog. Spread Spectrum Clock Synthesizer
Pin Assignment
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GND
S0
S1
VDD
VDDO1
CLK1
CLK2
CLK3
GND
X1/ICLK
S2
VDD
PDTS
GND
CLK6
CLK5
CLK4
VDDO2
VDD
X2
20 pin (173 mil) TSSOP
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin
Name
GND
S0
S1
VDD
VDDO1
CLK1
CLK2
CLK3
GND
X1/ICLK
X2
VDD
VDDO2
CLK4
CLK5
CLK6
GND
PDTS
VDD
S2
Pin
Type
Power
Input
Input
Power
Power
Output
Output
Output
Power
XI
XO
Power
Power
Output
Output
Output
Power
Input
Power
Input
Connect to ground.
Pin Description
Select pin 0. Internal pull-up resistor.
Select pin 1. Internal pull-up resistor.
Connect to +3.3 V.
Power supply for outputs CLK1-CLK3.
Output clock 1. Weak internal pull-down when tri-state.
Output clock 2. Weak internal pull-down when tri-state.
Output clock 3. Weak internal pull-down when tri-state.
Connect to ground.
Crystal input. Connect this pin to a crystal or external input clock.
Crystal Output. Connect this pin to a crystal. Float for clock input.
Connect to +3.3 V.
Power supply for outputs CLK4-CLK6.
Output clock 4. Weak internal pull-down when tri-state.
Output clock 5. Weak internal pull-down when tri-state.
Output clock 6. Weak internal pull-down when tri-state.
Connect to ground.
Power-down tri-state. Powers down entire chip and tri-states clock outputs
when low. Internal pull-up resistor.
Connect to +3.3 V.
Select pin 2. Internal pull-up resistor.
MDS 291 C
Integrated Circuit Systems, Inc.
●
2
525 Race Street, San Jose, CA 95126
●
Revision 062205
tel (408) 297-1201
●
www.icst.com
PRELIMINARY INFORMATION
ICS291
Triple PLL Field Prog. Spread Spectrum Clock Synthesizer
External Components
The ICS291 requires a minimum number of external
components for proper operation.
set within the range of M = 1 to 1024 and N = 1 to
32,895.
The ICS291 also provides separate output divide
values, from 2 through 63, to allow the two output clock
banks to support widely differing frequency values from
the same PLL.
Each output frequency can be represented as:
OutputFreq
----
-
⋅
M
N
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω.
=
REFFreq
Output Drive Control
The ICS291 has two output drive settings. For
VDDO=VDD, low drive should be selected when
outputs are less than 100 MHz. High drive should be
selected when outputs are greater than 100 MHz.
For VDDO<2.8 V, high drive should be selected for all
output frequencies.
(Consult the AC Electrical Characteristics for output
rise and fall times for each drive option.)
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
ICS291 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane. For
optimum device performance, the decoupling capacitor
should be mounted on the component side of the PCB.
Avoid the use of vias on the decoupling circuit.
ICS VersaClock Software
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
been the crystal and device. Crystal capacitors must be
connected from each of the pins X1 and X2 to ground.
The value (in pF) of these crystal caps should equal
(C
L
-6 pF)*2. In this equation, C
L
= crystal load
capacitance in pF. Example: For a crystal with a 16 pF
load capacitance, each crystal capacitor would be 20
pF [(16-6) x 2] = 20.
ICS applies years of PLL optimization experience into a
user friendly software that accepts the user’s target
reference clock and output frequencies and generates
the lowest jitter, lowest power configuration, with only a
press of a button. The user does not need to have prior
PLL experience or determine the optimal VCO
frequency to support multiple output frequencies.
VersaClock software quickly evaluates accessible VCO
frequencies with available output divide values and
provides an easy to understand, bar code rating for the
target output frequencies. The user may evaluate
output accuracy, performance trade-off scenarios in
seconds.
Spread Spectrum Modulation
The ICS291 utilizes frequency modulation (FM) to
distribute energy over a range of frequencies. By
modulating the output clock frequencies, the device
effectively lowers energy across a broader range of
frequencies; thus, lowering a system’s electromagnetic
interference (EMI). The modulation rate is the time from
transitioning from a minimum frequency to a maximum
frequency and then back to the minimum.
ICS291 Configuration Capabilities
The architecture of the ICS291 allows the user to easily
configure the device to a wide range of output
frequencies, for a given input reference frequency.
The frequency multiplier PLL provides a high degree of
precision. The M/N values (the multiplier/divide values
available to generate the target VCO frequency) can be
MDS 291 C
Integrated Circuit Systems, Inc.
●
3
525 Race Street, San Jose, CA 95126
●
Revision 062205
tel (408) 297-1201
●
www.icst.com
PRELIMINARY INFORMATION
ICS291
Triple PLL Field Prog. Spread Spectrum Clock Synthesizer
Spread Spectrum Modulation can be applied as either
“center spread” or “down spread”. During center spread
modulation, the deviation from the target frequency is
equal in the positive and negative directions. The
effective average frequency is equal to the target
frequency. In applications where the clock is driving a
component with a maximum frequency rating, down
spread should be applied. In this case, the maximum
frequency, including modulation, is the target
frequency. The effective average frequency is less than
the target frequency.
The ICS291 operates in both center spread and down
spread modes. For center spread, the frequency can
be modulated between ±0.125% to ±2.0%. For down
spread, the frequency can be modulated between
-0.25% to -4.0%.
Both output frequency banks will utilize identical spread
spectrum percentage deviations and modulation rates,
if a common VCO frequency can be identified.
Spread Spectrum Modulation Rate
The spread spectrum modulation frequency applied to
the output clock frequency may occur at a variety of
rates. For applications requiring the driving of
“down-circuit” PLLs, Zero Delay Buffers, or those
adhering to PCI standards, the spread spectrum
modulation rate should be set to 30-33 kHz. For other
applications, a 120 kHz modulation option is available.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS291. These ratings, which
are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Parameter
Supply Voltage, VDD
Inputs
Clock Outputs
Storage Temperature
Soldering Temperature
Junction Temperature
Condition
Referenced to GND
Referenced to GND
Referenced to GND
Max 10 seconds
Min.
-0.5
-0.5
-65
Typ.
Max.
7
VDD+0.5
VDD+0.5
150
260
125
Units
V
V
V
°C
°C
°C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature (ICS291GP)
Ambient Operating Temperature (ICS291GIP)
Power Supply Voltage (measured in respect to GND)
Power Supply Ramp Time
Min.
0
-40
+3.135
Typ.
Max.
+70
+85
Units
°C
°C
V
ms
+3.3
+3.465
4
MDS 291 C
Integrated Circuit Systems, Inc.
●
4
525 Race Street, San Jose, CA 95126
●
Revision 062205
tel (408) 297-1201
●
www.icst.com
PRELIMINARY INFORMATION
ICS291
Triple PLL Field Prog. Spread Spectrum Clock Synthesizer
DC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V ±5%,
Ambient Temperature -40 to +85°C
Parameter
Operating Voltage
VDDO Voltage
Symbol
VDD
Conditions
VDDO1 and VDDO2
Config. Dependent - See
VersaClock
TM
Estimates
Min.
3.135
1.80
Typ.
Max.
3.465
VDD
Units
V
V
mA
Operating Supply Current
IDD
Six 33.3333 MHz outs,
VDD=VDDO=3.3 V;
PDTS = 1, no load, Note 1
PDTS = 0, no load
S2:S0
S2:S0
VDD-0.5
VDD/2+1
25
mA
500
0.4
0.4
Input High Voltage
Input Low Voltage
Input High Voltage, PDTS
Input Low Voltage, PDTS
Input High Voltage
Input Low Voltage
Output High Voltage
(CMOS High)
Output High Voltage
Output Low Voltage
Short Circuit Current
Nom. Output Impedance
Internal Pull-up Resistor
Internal Pull-down
Resistor
Input Capacitance
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OH
V
OL
I
OS
Z
O
R
PUS
R
PD
C
IN
µA
V
V
V
V
V
VDD/2-1
V
V
V
0.4
V
ICLK
ICLK
I
OH
= -4 mA
I
OH
= -8 mA (Low Drive);
I
OH
= -12 mA (High Drive)
I
OL
= 8 mA (Low Drive);
I
OL
= 12 mA (High Drive)
Low Drive
High Drive
S2:S0, PDTS
CLK outputs
Inputs
VDD/2+1
VDD-0.4
2.4
VDDO-0.4
±40
±70
20
190
120
4
mA
Ω
kΩ
kΩ
pF
Note 1: Example with 25 MHz crystal input with six outputs of 33.3 MHz, no load, and VDD = 3.3 V.
MDS 291 C
Integrated Circuit Systems, Inc.
●
5
525 Race Street, San Jose, CA 95126
●
Revision 062205
tel (408) 297-1201
●
www.icst.com
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