Integrated
Circuit
Systems, Inc.
ICS8745B
1:5 D
IFFERENTIAL
-
TO
-LVDS
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
F
EATURES
•
5 differential LVDS outputs designed to meet
or exceed the requirements of ANSI TIA/EIA-644
•
Selectable differential clock inputs
•
CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
•
Output frequency range: 31.25MHz to 700MHz
•
Input frequency range: 31.25MHz to 700MHz
•
VCO range: 250MHz to 700MHz
•
External feedback for “zero delay” clock regeneration
with configurable frequencies
•
Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
•
Cycle-to-cycle jitter: 30ps (maximum)
•
Output skew: 35ps (maximum)
•
Static phase offset: 25ps ± 125ps
•
3.3V supply voltage
•
0°C to 70°C ambient operating temperature
•
Lead-Free package fully RoHS compliant
G
ENERAL
D
ESCRIPTION
The ICS8745B is a highly versatile 1:5 LVDS Clock
Generator and a member of the HiPerClockS™
HiPerClockS™
family of High Performance Clock Solutions from
ICS. The ICS8745B has a fully integrated PLL
and can be configured as zero delay buffer, multi-
plier or divider, and has an output frequency range of 31.25MHz
to 700MHz. The Reference Divider, Feedback Divider and
Output Divider are each programmable, thereby allowing for
the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8. The external feedback allows the device to achieve
“zero delay” between the input clock and the output clocks.
The PLL_SEL pin can be used to bypass the PLL for system
test and debug purposes. In bypass mode, the reference clock
is routed around the PLL and into the internal output dividers.
ICS
B
LOCK
D
IAGRAM
PLL_SEL
÷1, ÷2, ÷4, ÷8,
÷16, ÷32
,
÷64
0
1
CLK1
nCLK1
CLK_SEL
FB_IN
nFB_IN
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
1
0
P
IN
A
SSIGNMENT
Q0
nQ0
V
DD
PLL_SEL
SEL3
GND
V
DDO
V
DDA
nQ4
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
CLK0
nCLK0
32 31 30 29 28 27 26 25
SEL0
SEL1
CLK0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
V
DD
nFB_IN
FB_IN
SEL2
GND
nQ0
Q0
V
DDO
24
23
22
Q3
nQ3
V
DDO
Q2
nQ2
GND
Q1
nQ1
PLL
Q4
nQ4
nCLK0
CLK1
nCLK1
CLK_SEL
MR
ICS8745B
21
20
19
18
17
SEL0
SEL1
SEL2
SEL3
MR
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
www.icst.com/products/hiperclocks.html
1
REV. B DECEMBER 2, 2004
8745BY
Integrated
Circuit
Systems, Inc.
ICS8745B
1:5 D
IFFERENTIAL
-
TO
-LVDS
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
Type
Description
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
5
6
7
Name
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
Input
Input
Input
Input
Input
Input
Input
Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Pulldown Non-inver ting differential clock input.
Pullup
Pullup
Inver ting differential clock input.
Pulldown Non-inver ting differential clock input.
Inver ting differential clock input.
Clock select input. When HIGH, selects CLK1, nCLK1.
Pulldown
When LOW, selects CLK0, nCLK0. LVCMOS / LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inver ted outputs nQx to go
Pulldown
high. When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS / LVTTL interface levels.
Core supply pins.
Pullup
Feedback input to phase detector for regenerating clocks with "zero delay".
Pulldown Feedback input to phase detector for regenerating clocks with "zero delay".
Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Power supply ground.
Differential output pair. LVDS interface levels.
Output supply pins.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Analog supply pin.
Selects between the PLL and reference clock as the input to the dividers.
When LOW, selects reference clock. LVCMOS / LVTTL interface levels.
8
9, 32
10
11
12
13, 19, 25
14, 15
16, 22, 28
17, 18
20, 21
23, 24
26, 27
29
30
31
MR
V
DD
nFB_IN
FB_IN
SEL2
GND
nQ0, Q0
V
DDO
nQ1, Q1
nQ2, Q2
nQ3, Q3
nQ4, Q4
SEL3
V
DDA
PLL_SEL
Input
Power
Input
Input
Input
Power
Output
Power
Output
Output
Output
Output
Input
Power
Input
Pullup
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
8745BY
www.icst.com/products/hiperclocks.html
2
REV. B DECEMBER 2, 2004
Integrated
Circuit
Systems, Inc.
ICS8745B
1:5 D
IFFERENTIAL
-
TO
-LVDS
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
Outputs
PLL_SEL = 1
PLL Enable Mode
Q0:Q4, nQ0:nQ4
÷1
÷1
÷1
÷1
÷2
÷2
÷2
÷4
÷4
÷8
x2
x2
x2
x4
x4
x8
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
SEL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Reference Frequency Range (MHz)*
250 - 700
125 - 350
62.5 - 175
31.25 - 87.5
250 - 700
125 - 350
62.5 - 175
250 -700
125 - 350
250 - 700
125 - 350
62.5 - 175
31.25 - 87.5
62.5 - 175
31.25 - 87.5
31.25 - 87.5
*NOTE: VCO frequency range for all configurations above is 250MHz to 700MHz.
T
ABLE
3B. PLL B
YPASS
F
UNCTION
T
ABLE
Inputs
SEL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
8745BY
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Outputs
PLL_SEL = 0
PLL Bypass Mode
Q0:Q4, nQ0:nQ4
÷4
÷4
÷4
÷8
÷8
÷8
÷ 16
÷ 16
÷ 32
÷ 64
÷2
÷2
÷4
÷1
÷2
÷1
REV. B DECEMBER 2, 2004
www.icst.com/products/hiperclocks.html
3
Integrated
Circuit
Systems, Inc.
ICS8745B
1:5 D
IFFERENTIAL
-
TO
-LVDS
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
125
17
59
Units
V
V
V
mA
mA
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol Parameter
V
IH
V
IL
I
IH
Input High Voltage
Input Low Voltage
Input High Current
CLK_SEL, MR, SEL0,
SEL1, SEL2, SEL3
PLL_SEL
CLK_SEL, MR, SEL0,
SEL1, SEL2, SEL3
PLL_SEL
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
I
IL
Input Low Current
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol Parameter
I
IH
I
IL
V
PP
V
CMR
Input
High Current
Input
Low Current
CLK0, CLK1, FB_IN
nCLK0, nCLK1, nFB_IN
CLK0, CLK1, FB_IN
nCLK0, nCLK1, nFB_IN
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
0.15
GND + 0.5
1.3
V
DD
- 0.85
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for CLK0, nCLK0 and CLK1, nCLK1 is V
DD
+ 0.3V.
8745BY
www.icst.com/products/hiperclocks.html
4
REV. B DECEMBER 2, 2004
Integrated
Circuit
Systems, Inc.
ICS8745B
1:5 D
IFFERENTIAL
-
TO
-LVDS
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
Test Conditions
Minimum
320
1.05
Typical
440
0
1.2
Maximum
550
50
1.35
25
Units
mV
mV
V
mV
T
ABLE
4D. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
OD
Δ
V
OD
V
OS
Δ
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
T
ABLE
5. I
NPUT
F
REQUENCY
C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
f
IN
Parameter
Input Frequency
CLK0, nCLK0,
CLK1, nCLK1
Test Conditions
PLL_SEL = 1
PLL_SEL = 0
Minimum
31.25
Typical
Maximum
700
70 0
Units
MHz
MHz
T
ABLE
6. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
f
MAX
t
PD
Parameter
Output Frequency
Propagation Delay; NOTE 1
Static Phase Offset; NOTE 2, 5
Output Skew; NOTE 3, 5
Cycle-to-Cycle Jitter ; NOTE 5, 6
Phase Jitter ; NOTE 4, 5, 6
Output Duty Cycle
PLL Lock Time
46
50
PLL_SEL = 0V, f
≤
700MHz
PLL_SEL = 3.3V
3.1
-100
3.4
25
Test Conditions
Minimum
Typical
Maximum
700
3.7
150
35
30
±52
54
1
700
Units
MHz
ns
ps
ps
ps
ps
%
ms
ps
t
sk(Ø)
t
sk(o)
t
jit(cc)
t
jit(
θ)
odc
t
L
t
R
/ t
F
Output Rise/Fall Time; NOTE 7
200
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback
input signal across all conditions, when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Characterized at VCO frequency of 622MHz.
NOTE 7: Measured from the 20% to 80% points. Guaranteed by characterization. Not production tested.
8745BY
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5
REV. B DECEMBER 2, 2004
