Integrated
Circuit
Systems, Inc.
ICS9248-101
Frequency Generator & Integrated Buffers for PENTIUM/Pro
TM
& K6
General Description
The
ICS9248-101
is the single chip clock solution for
Notebook designs using the 440BX or the VIA Apollo Pro 133
style chipset. It provides all necessary clock signals for such a
system.
Spread spectrum may be enabled through I
2
C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The
ICS9248-101
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Features
Up to 137MHz frequency support
Spread Spectrum for EMI control
Serial I
2
C interface for Power Management,
Frequency Select, Spread Spectrum.
Provides the following system clocks
- 4-CPUs @ 2.5/3.3V, up to 137MHz.
(including CPUCLK_F)
- 9-SDRAMs @3.3V, up to 137MHz
(including SDRAM_F)
- 8-PCI @3.3V, CPU/2 or CPU/3
(including 1 free running PCICLK_F)
- 1-24/48MHz @3.3V
- 1-48MHz @3.3V fixed
- 2-REF @3.3V, 14.318MHz.
Efficient Power management scheme through PCI
and STOP CLOCKS
Spread Spectrum ± .25%, & 0 to -0.5% down spread
Block Diagram
Pin Configuration
VDDREF
REF0
GNDREF
X1
X2
VDDPCI
*CPU2.5_3.3#/PCICLK_F
*FS3/PCICLK0
GNDPCI
*SEL24_48#/PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDPCI
BUFFER IN
GNDPCI
PCICLK5
PCICLK6
VDDCOR
PCI_STOP#
*PD#
GND48
SDATA
2
I C
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF1/FS2*
VDDLCPU
CPUCLK_F
CPUCLK0
GNDLCPU
CPUCLK1
CPUCLK2
CLK_STOP#
GNDSDR
SDRAM_F
SDRAM0
SDRAM1
VDDSDR
SDRAM2
SDRAM3
GNDSDR
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
VDD48
48MHz/FS0*
24_48MHz/FS1*
{
Power Groups
VDDLCPU, GNDLCPU = CPUCLK [2:0], CPUCLK_F
VDDSDR, GNDSDR = SDRAMCLKS [7:0], SDRAM_F
VDDPCI, GNDPCI = PCICLKS [6:0], PCICLK_F
VDD48, GND48 = 48MHz, 24MHz
VDDREF, GNDREF = REF, X1, X2
VDDCOR = PLL CORE
9248-101 Rev C 2/29/00
48-Pin SSOP and TSSOP
* Internal Pull-up Resistor of 120K to VDD
Pentium is a trademark of Intel Corporation
I
2
C is a trademark of Philips Corporation
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
ICS9248-101
ICS9248-101
Pin Descriptions
PIN
NUMBER
1
2
20
3, 9, 16,
33, 40, 44
4
5
6,14
7
8
10
18, 17, 13,
12, 11,
15
19
21
22
28, 29, 31, 32,
34, 35, 37, 38
30, 36
23
24
25
26
27
39
41
42, 43, 45
46
47
48
P I N NA M E
VDDREF
REF0
PCI_STOP#
GND
X1
X2
VDDPCI
C P U 2 . 5 _ 3 . 3 #
1,2
PCICLK_F
FS3
1,2
PCICLK0
SEL24_48#
PCICLK1
1,2
TYPE
PWR
OUT
IN
PWR
IN
OUT
PWR
IN
OUT
IN
OUT
IN
OUT
OUT
IN
PWR
IN
PWR
OUT
PWR
IN
IN
OUT
IN
OUT
IN
PWR
OUT
IN
OUT
OUT
PWR
OUT
IN
DESCRIPTION
Ref, XTAL power supply, nominal 3.3V
14.318 Mhz reference clock.This REF output is the STRONGER buffer for ISA BUS loads
Halts PCICLK [6:0]clocks at logic 0 level, when input low (In mobile mode, MODE=0)
Ground
Crystal input, has internal load cap (36pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz.
Supply for PCICLK_F and PCICLK [6:0], nominal 3.3V
Indicates whether VDDLCPU is 2.5 or 3.3V. High=2.5V CPU, LOW=3.3V CPU. Latched Input.
Free running PCI clock not affected by PCI_STOP# for power management.
Frequency select pin. Latched Input.
PCI clock output. Synchronous to CPU clocks with 1-4ns skew (CPU early)
Selects either 24 or 48MHz when Low =48 MHz
PCI clock output. Synchronous to CPU clocks with 1-4ns skew (CPU early)
PCI clock outputs. Synchronous to CPU clocks with 1-4ns skew (CPU early)
Input to Fanout Buffers for SDRAM outputs.
Power pin for the PLL core. 3.3V
Asynchronous active low input pin used to power down the device into a low power state. The
internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power
down will not be greater than 4ms.
Ground pin for the 24 & 48MHz output buffers & fixed PLL core.
SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin (controlled by chipset).
Supply for SDRAM [7:0] and CPU PLL Core, nominal 3.3V.
Data input for I
2
C serial input, 5V tolerant input
Clock input of I
2
C input, 5V tolerant input
24MHz or 48MHz output clock selectable by pin 10
Frequency select pin. Latched Input.
48MHz output clock
Frequency select pin. Latched Input
Power for 24 & 48MHz output buffers and fixed PLL core.
Free running SDRAM clock output. Not affected by CPU_STOP#
This asynchronous input halts CPUCLK(0:2), & SDRAM (0:7) at logic "0" level when driven low.
CPU clock outputs, powered by VDDLCPU
Free running CPU clock. Not affected by the CPU_STOP#
Supply for CPU clocks 2.5V
14.318 MHz reference clock.
Frequency select pin. Latched Input
PCICLK [6:2]
BUFFER IN
VDDCOR
PD#
1
GND48
SDRAM [7:0]
VDDSDR
SDATA
SCLK
24_48MHz
FS1
1, 2
48MHz
FS0
1, 2
VDD48
SDRAM_F
CLK_STOP#
CPUCLK [2:0]
CPUCLK_F
VDDLCPU
REF1
FS2
1, 2
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
2
ICS9248-101
The information in this section assumes familiarity with I
2
C programming.
For more information, contact ICS for an I
2
C programming application note.
General I
2
C serial interface information
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends a dummy command code
ICS clock will
acknowledge
Controller (host) sends a dummy byte count
ICS clock will
acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock will
acknowledge
each byte
one at a time.
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the
byte count
Controller (host) acknowledges
ICS clock sends first byte
(Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
How to Write:
Controller (Host)
Start Bit
Address
D2
(H)
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
ACK
Stop Bit
ACK
Byte 5
ACK
Byte 4
ACK
Byte 3
ACK
Byte 2
ACK
Byte 1
ACK
Byte 0
ICS (Slave/Receiver)
How to Read:
Controller (Host)
Start Bit
Address
D3
(H)
ICS (Slave/Receiver)
ACK
ACK
Byte Count
Notes:
1.
2.
3.
4.
5.
6.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches for verification.
Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
3
ICS9248-101
Functionality
V
DD
= 3.3V±5%, V
DDL
= 2.5V±5% or 3.3±5%, TA=0 to 70°C
Crystal (X1, X2) = 14.31818MHz
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
(MHz)
124.00
120.00
114.99
109.99
105.00
83.31
137.00
75.00
100.00
95.00
83.31
133.33
90.00
96.22
66.82
91.5
PCI
(MHz)
41.33
40.00
38.33
36.66
35.00
41.65
34.25
37.50
33.33
31.67
27.77
33.33
30.00
32.07
33.41
30.5
Serial Configuration Command Bitmap
Bit
Bit 7
Byte0: Functionality and Frequency Select Register (default = 0)
Description
0 - ±0.25% Spread Spectrum Modulation, Center Spread
1 - 0 to -0.5% Down Spread
CPUCLK
PCICLK
Bit [2, 6:4]
(MHz)
(MHz)
0000
124.00
41.33
0001
120.00
40.00
0010
114.99
38.33
0011
109.99
36.66
0100
105.00
35.00
0101
83.31
41.65
0110
137.00
34.25
0111
75.00
37.50
1000
100.00
33.33
1001
95.00
31.67
1010
83.31
27.77
1011
133.33
33.33
1100
90.00
30.00
1101
96.22
32.07
1110
66.82
33.41
1111
91.5
30.5
0 - Frequency is selected by hardware select, latched inputs
1 - Frequency is selected by Bit [2, 6:4]
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
1- Tristate all outputs
PWD
1
Bit
[2, 6:4]
Note1
Bit 3
Bit 1
Bit 0
0
1
0
Notes:
1, Default at Power-up will be for latched
logic inputs to define frequency. Bit [2,
6:4] are default to 0010.
2, PWD = Power-Up Default
3, When disabling spread spectrum bit7
needs to be set to 0 to maintain nominal
frequency.
4
ICS9248-101
Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
46
-
-
39
42
43
45
PWD
1
1
1
1
1
1
1
1
Description
(Reserved)
CPUCLK_F (Act/Inact)
(Reserved)
(Reserved)
SDRAM_F (Act/Inact)
CPUCLK2 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK0 (Act/Inact)
Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
7
18
17
13
12
11
10
8
PWD
1
1
1
1
1
1
1
1
Description
PCICLK_F (Act/Inact)
PCICLK6 (Act/Inact)
PCICLK5 (Act/Inact)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0 (Act/Inact)
Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
-
-
28
29
31
32
PWD
1
1
1
1
1
1
1
1
Description
(Reserved)
(Reserved)
(Reserved)
(Reserved)
SDRAM7 (Active/Inactive)
SDRAM6 (Active/Inactive)
SDRAM5 (Active/Inactive)
SDRAM4 (Active/Inactive)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
5
