Integrated
Circuit
Systems, Inc.
ICS950211
Programmable Timing Control Hub™ for P4™
Recommended Application:
Brookdale and Brookdale -G chipset with P4 processor.
Output Features:
•
3 - Pairs of differential CPU clocks (differential current mode)
•
5 - 3V66 @ 3.3V
•
10 - PCI @ 3.3V
•
2 - 48MHz @ 3.3V fixed
•
1 - REF @ 3.3V, 14.318MHz
•
1 - VCH/3V66 @ 3.3V, 48 MHz or 66.6 MHz
Features/Benefits:
•
Programmable output frequency.
•
Programmable output divider ratios.
•
Programmable output rise/fall time.
•
Programmable output skew.
•
Programmable spread percentage for EMI control.
•
Watchdog timer technology to reset system
if system malfunctions.
•
Programmable watch dog safe frequency.
•
Support I
2
C Index read/write and block read/write operations.
•
Uses external 14.318MHz crystal.
Key Specifications:
•
CPU Output Jitter <150ps
•
3V66 Output Jitter <250ps
•
CPU Output Skew <100ps
Pin Configuration
VDDREF
X1
X2
GND
1
PCICLK_F0
1
PCICLK_F1
PCICLK_F2
VDDPCI
GND
1
*WDEN/PCICLK0
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
PCICLK4
PCICLK5
PCICLK6
VDD3V66
GND
3V66_2
3V66_3
3V66_4
3V66_5
*PD#
VDDA
GND
*Vtt_PWRGD#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
REF
FS1
FS0
CPU_STOP#*
CPUCLKT0
CPUCLKC0
VDDCPU
CPUCLKT1
CPUCLKC1
GND
VDDCPU
CPUCLKT2
CPUCLKC2
MULTSEL0*
I REF
GND
FS2
48MHz_USB/FS3**
48MHz_DOT
AVDD48
GND
3V66_1/VCH_CLK/FS4**
PCI_STOP#*
3V66_0
VDD
GND
SCLK
SDATA
1
56-Pin 300-mil SSOP & 240-mil TSSOP
1. These outputs have 2X drive strength.
* Internal Pull-up resistor of 120K to VDD
** these inputs have 120K internal pull-down
to GND
Block Diagram
PLL2
48MHz_USB
48MHz_DOT
X1
X2
XTAL
OSC
3V66_1/VCH_CLK
REF
PLL1
Spread
Spectrum
WDEN
PD#
CPU_STOP#
PCI_STOP#
MULTSEL0
FS (4:0)
SDATA
SCLK
Vtt_PWRGD#
CPU
DIVDER
Stop
3
3
Frequency Table
FS4 FS3 FS2 FS1 FS0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPUCLK
MHz
66.66*
100.00
200.00
133.33
100.90
105.00
109.00
114.00
117.00
127.00
130.00
132.50
205.00
170.00
180.00
190.00
3V66
MHz
66.66
66.66
66.66
66.66
67.27
70.00
72.67
76.00
78.00
72.86
74.29
75.71
70.00
56.67
60.00
63.33
PCICLK
MHz
33.33
33.33
33.33
33.33
33.63
35.00
36.33
38.00
39.00
36.43
37.14
37.89
35.00
28.33
30.00
31.67
CPUCLKT (2:0)
CPUCLKC (2:0)
PCICLK (6:0)
PCICLK_F (2:0)
PCI
DIVDER
Stop
7
3
Control
Logic
3V66
DIVDER
5
3V66 (5:2, 0)
I REF
Config.
Reg.
For additional frequency selections please refer to Byte 0.
*
For 950211BF version, this frequency is 166.66MHz.
Power Groups
0465E—05/17/05
VDDA = Analog Core PLL
VDDREF = REF, Xtal
AVDD48 = 48MHz
ICS950211
Integrated
Circuit
Systems, Inc.
ICS950211
General Description
The
ICS950211
is a single chip clock solution for desktop designs using the Intel Brookdale chipset with PC133 or DDR
memory. It provides all necessary clock signals for such a system.
The
ICS950211
is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). This part
incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a
serially programmable I
2
C interface, this device can adjust the output clocks by configuring the frequency setting, the output
divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Pin Description
PIN NUMBER
1, 8, 14, 19,
32, 46, 50
2
3
4, 9, 15, 20, 27, 31,
36, 41, 47
24, 23, 22, 21, 33
7,6,5
10
VDD
X1
X2
GND
3V66 (5:2, 0)
PCICLK_F(2:0)
WDEN
PCICLK0
PIN NAME
TYPE
PWR
IN
OUT
PWR
OUT
OUT
IN
OUT
OUT
IN
PWR
IN
IN
I/O
IN
OUT
IN
PWR
OUT
IN
OUT
OUT
IN
OUT
OUT
IN
IN
OUT
3.3V power supply.
Cr ystal input, has inter nal load cap (33pF) and feedback resistor from X2.
Cr ystal output, nominally 14.318MHz. Has inter nal load cap (33pF).
Ground pins for 3.3V supply.
3.3V Fixed 66MHz clock outputs for HUB.
3.3V PCI clock output
Hardware enable of watch dog circuit. Enabled when latched high.
3.3V PCI clock output.
3.3V PCI clock outputs.
Asynchronous active low input pin used to power down the device into a low
power state. The inter nal clocks are disabled and the VCO and the cr ystal are
s t o p p e d . T h e l a t e n c y o f t h e p ow e r d ow n w i l l n o t b e g r e a t e r t h a n 3 m s.
Analog power 3.3V.
This 3.3V LVTTL input is a level sensitive strobe used to determine when FS (4:0)
inputs are valid and are ready to be sampled (active low).
Clock pin for I
2
C circuitr y 5V tolerant.
Data pin for I
2
C circuitr y 5V tolerant.
Halts PCICLK clocks at logic 0 level, when input low except PCICLK_F which are
free running.
3.3V output selectable through I
2
C to be 66MHz from internal VCO or
48MHz (non-SSC).
L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n .
Analog power 3.3V.
3.3V Fixed 48MHz clock output for DOT.
L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n .
3.3V Fixed 48MHz clock output for USB.
This pin establishes the reference current for the CPUCLK pairs. This pin requires
a fixed precision resistor tied to ground in order to establish the appropriate
current.
3.3V LVTTL input for selecting the current multiplier for CPU outputs
"Complementor y" clocks of differential pair CPU outputs. These are current
outputs and external resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current outputs and
external resistors are required for voltage bias.
L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n .
Halts CPUCLK clocks at logic 0 level, when input low except CPUCLK_F which
are free running.
3.3V, 14.318MHz reference clock output.
DESCRIPTION
18, 17, 16, 13, 12, 11 PCICLK (6:1)
25
26
28
30
29
34
35
37
38
39
42
43
44, 48, 51
45, 49, 52
40, 55, 54
53
56
PD#
VDDA
Vtt_PWRGD#
SCLK
SDATA
PCI_STOP#
3V66_1/VCH_CLK
FS4
AVDD48
48MHz_DOT
FS3
48MHz_USB
I REF
MULTSEL0
CPUCLKC (2:0)
CPUCLKT (2:0)
FS (2:0)
CPU_STOP#
REF
0465E—05/17/05
2
Integrated
Circuit
Systems, Inc.
ICS950211
Maximum Allowed Current
Max 3.3V supply consumption
Max discrete cap loads,
Vdd = 3.465V
All static inputs = Vdd or GND
40mA
360mA
Condition
Powerdown Mode
(PWRDWN# = 0)
Full Active
Host Swing Select Functions
MULTISEL0
Board Target
Trace/Term Z
50 ohms
50 ohms
Reference R,
Iref =
V
DD
/(3*Rr)
Rr = 221 1%,
Iref = 5.00mA
Rr = 475 1%,
Iref = 2.32mA
Output
Current
Ioh = 4* I REF
Ioh = 6* I REF
Voh @ Z
0
1
1.0V @ 50
0.7V @ 50
0465E—05/17/05
3
Integrated
Circuit
Systems, Inc.
ICS950211
General I
2
C serial interface information
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte location = N
ICS clock will
acknowledge
Controller (host) sends the data byte count = X
ICS clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the data byte count = X
ICS clock sends
Byte N + X -1
ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D2
(H)
WR
WRite
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host)
T
starT bit
Slave Address D2
(H)
WR
WRite
Beginning Byte = N
ACK
RT
Repeat starT
Slave Address D3
(H)
RD
ReaD
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
*See notes on the following page
.
0465E—05/17/05
4
Integrated
Circuit
Systems, Inc.
ICS950211
Byte 0: Functionality and frequency select register (Default=0)
Bit
Description
Bit2 Bit7 Bit6 Bit5 Bit4 CPUCLK
MHz
FS4 FS3 FS2 FS1 FS0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0-
1-
0-
1-
0-
1-
3V66
MHz
PCICLK
MHz
Spread %
PWD
Bit
(2,7:4)
Bit 3
Bit 1
Bit 0
0
0
0
0
66.66
2
66.66
33.33
0 to -0.5% down spread
0
0
0
1
100.00
66.66
33.33
0 to -0.5% down spread
0
0
1
0
200.00
66.66
33.33
0 to -0.5% down spread
33.33
0 to -0.5% down spread
0
0
1
1
133.33
66.66
0
1
0
0
100.90
67.27
33.63
+/-0.35% center spread
0
1
0
1
105.00
70.00
35.00
+/-0.35% center spread
+/-0.35% center spread
0
1
1
0
109.00
72.67
36.33
0
1
1
1
114.00
76.00
38.00
+/-0.35% center spread
1
0
0
0
117.00
78.00
39.00
+/-0.35% center spread
+/-0.35% center spread
1
0
0
1
127.00
72.86
36.43
1
0
1
0
130.00
74.29
37.14
+/-0.35% center spread
1
0
1
1
132.50
75.71
37.89
+/-0.35% center spread
+/-0.35% center spread
1
1
0
0
205.00
70.00
35.00
1
1
0
1
170.00
56.67
28.33
+/-0.35% center spread
1
1
1
0
180.00
60.00
30.00
+/-0.35% center spread
+/-0.35% center spread
1
1
1
1
190.00
63.33
31.67
0
0
0
0
133.90
66.95
33.48
+/-0.35% center spread
0
0
0
1
133.33
66.67
33.33
+/-0.35% center spread
+/-0.35% center spread
0
0
1
0
120.00
60.00
30.00
0
0
1
1
125.00
62.50
31.25
+/-0.35% center spread
0
1
0
0
134.90
67.45
33.73
+/-0.35% center spread
+/-0.35% center spread
0
1
0
1
137.00
68.50
34.25
0
1
1
0
139.00
69.50
34.75
+/-0.35% center spread
0
1
1
1
141.00
70.50
35.25
+/-0.35% center spread
+/-0.35% center spread
1
0
0
0
143.00
71.50
35.75
1
0
0
1
145.00
72.50
36.25
+/-0.35% center spread
1
0
1
0
150.00
75.00
37.50
+/-0.35% center spread
+/-0.35% center spread
1
0
1
1
155.00
77.50
38.75
1
1
0
0
160.00
80.00
40.00
+/-0.35% center spread
1
1
0
1
150.00
64.29
32.14
+/-0.35% center spread
1
1
1
0
160.00
68.57
34.29
+/-0.35% center spread
1
1
1
1
170.00
72.86
36.43
+/-0.35% center spread
Frequency is selected by hardware select, latched inputs
Frequency is selected by Bit 2,7:4
Normal
Spread spectrum enable
Watch dog safe frequency will be selected by latch inputs
Watch dog safe frequency will be programmed by Byte 10 bit (4:0)
Note 1
0
1
0
Notes:
1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
2. For 950211BF version, this frequency is 166.66MHz.
0465E—05/17/05
5
嵌入式系统
