DATASHEET
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Description
The
ICS9FG104
is a Frequency Timing Generator that provides 4
differential output pairs that are compliant to the Intel CK410
specification. It also provides support for PCI-Express and SATA.
The part synthesizes several output frequencies from either a
14.31818 Mhz crystal or a 25 MHz crystal. The device can also be
driven by a reference input clock instead of a crystal. It provides
outputs with cycle-to-cycle jitter of less than 50 ps and output-to-
output skew of less than 35 ps. The
ICS9FG104
also provides a copy
of the reference clock. Frequency selection can be accomplished via
strap pins or SMBus control.
ICS9FG104
Features/Benefits
•
•
•
•
•
•
•
Generates common frequencies from 14.318 MHz or
25 MHz
Crystal or reference input
4 - 0.7V current-mode differential output pairs
Supports Serial-ATA at 100 MHz
Two spread spectrum modes: 0 to -0.5 downspread
and +/-0.25% centerspread
Unused inputs may be disabled in either driven or Hi-Z
state for power management.
M/N Programming
Key Specifications
•
•
•
•
•
•
Output cycle-to-cycle jitter < 50 ps
Output to output skew < 35 ps
+/-300 ppm frequency accuracy on output clocks
+/- 150 ppm frequency accuracy @ 100 MHz outputs
28-pin SSOP/TSSOP package
Available in RoHS compliant packaging
Funtional Block Diagram
XIN/CLKIN
OSC
X2
2
R EF OU T
PROGRAMMABLE
SPREAD PLL
STOP
LOGIC
4
DIF(3:0)
SPREAD
SEL14M_25M#
DIF_STOP#
FS(2:0)
SDATA
SCLK
CONTROL
LOGIC
IREF
IDT
TM
/ICS
TM
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
0839O—12/03/08
1
ICS9FG104
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Pin Configuration
XIN/CLKIN
X2
VDD
GND
REFOUT
**FS2
DIF_3
DIF_3#
VDD
GND
DIF_2
DIF_2#
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDDA
GNDA
IREF
**FS0
**FS1
DIF_0
DIF_0#
VDD
GND
DIF_1
DIF_1#
*SEL14M_25M#
**SPREAD
DIF_STOP#
Functionality Table
SEL14M_25M#
FS2 FS1 FS0 OUTPUT(MHz)
(FS3)
0
0
0
0
100.00
0
0
0
1
125.00
0
0
1
0
133.33
0
0
1
1
166.67
0
1
0
0
200.00
0
1
0
1
266.00
0
1
1
0
333.00
0
1
1
1
400.00
1
0
0
0
100.00
1
0
0
1
125.00
1
0
1
0
133.33
1
0
1
1
166.67
1
1
0
0
200.00
1
1
0
1
266.00
1
1
1
0
333.00
1
1
1
1
400.00
* Pin has internal 120K pull up
** Pin has internal 120K pull down
28-pin SSOP/TSSOP
Power Groups
Pin Number
VDD
GND
3
4
9,21
10,20
28
27
Description
REFOUT, Digital Inputs
DIF Outputs
IREF, Analog VDD, GND for PLL Core
IDT
TM
/ICS
TM
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG104
0839O—12/03/08
2
ICS9FG104
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Pin Description
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PIN NAME
XIN/CLKIN
X2
VDD
GND
REFOUT
**FS2
DIF_3
DIF_3#
VDD
GND
DIF_2
DIF_2#
SDATA
SCLK
DIF_STOP#
**SPREAD
*SEL14M_25M#
DIF_1#
DIF_1
GND
VDD
DIF_0#
DIF_0
**FS1
**FS0
IREF
GNDA
VDDA
PIN TYPE
IN
OUT
PWR
PWR
OUT
IN
OUT
OUT
PWR
PWR
OUT
OUT
I/O
IN
IN
IN
IN
OUT
OUT
PWR
PWR
OUT
OUT
I/O
IN
OUT
PWR
PWR
DESCRIPTION
Crystal input or Reference Clock input
Crystal output, Nominally 14.318MHz
Power supply, nominal 3.3V
Ground pin.
Reference Clock output
Frequency select pin.
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
Ground pin.
0.7V differential true clock output
0.7V differential Complementary clock output
Data pin for SMBus circuitry, 3.3V tolerant.
Clock pin of SMBus circuitry, 5V tolerant.
Active low input to stop differential output clocks.
Asynchronous, active high input to enable spread spectrum functionality.
Select 14.31818 MHz or 25 Mhz input frequency. 1 = 14.31818 MHz, 0 = 25 MHz
0.7V differential Complementary clock output
0.7V differential true clock output
Ground pin.
Power supply, nominal 3.3V
0.7V differential Complementary clock output
0.7V differential true clock output
Frequency select pin.
Frequency select pin.
This pin establishes the reference current for the differential current-mode output
pairs. This pin requires a fixed precision resistor tied to ground in order to establish
the appropriate current. 475 ohms is the standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
IDT
TM
/ICS
TM
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
0839O—12/03/08
3
ICS9FG104
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
General SMBus serial interface information for the ICS9FG104
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address DC
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte location = N
ICS clock will
acknowledge
Controller (host) sends the data byte count = X
ICS clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1
• ICS clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the write address DC
(h)
ICS clock will
acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address DD
(h)
ICS clock will
acknowledge
ICS clock will send the data byte count = X
ICS clock sends
Byte N + X -1
ICS clock sends
Byte 0 through byte X (if X
(h)
was written to byte 8)
.
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address DC
(h)
WR
WRite
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host)
T
starT bit
Slave Address DC
(h)
WR
WRite
Beginning Byte = N
ACK
RT
Repeat starT
Slave Address DD
(h)
RD
ReaD
ACK
Data Byte Count = X
ACK
Beginning Byte N
X Byte
ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
ACK
Byte N + X - 1
N
P
Not acknowledge
stoP bit
IDT
TM
/ICS
TM
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
0839O—12/03/08
4
ICS9FG104
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
SMBus Table: Device Control Register, READ/WRITE ADDRESS (DC/DD)
Byte 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
17
6
24
25
16
-
Name
FS3
1
Control Function
FS2
1
FS1
1
FS0
1
Spread Enable
1
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
Pin 17
Pin 6
Pin 24
Pin 25
Pin 16
0
0
0
See Frequency Selection Table,
Page 1
Off
On
Enable Software Control of Frequency, Spread Enable
(Spread Type always Software Control)
DIF_STOP# drive mode
SPREAD TYPE
Hardware Select Software Select
Driven
Down
Hi-Z
Center
Notes:
1. These bits reflect the state of the corresponding pins at power up, but may be written to
if Byte 0, bit 2 is set to '1'. FS3 is the SEL14M_25M# pin.
SMBus Table: Output Enable Register
Byte 1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
-
-
-
-
-
-
DIF_1 EN
DIF_0 EN
DIF_3 EN
DIF_2 EN
Name
Control Function
Reserved
Output Enable
Output Enable
Reserved
Reserved
Output Enable
Output Enable
Reserved
RW
RW
Disable
Disable
Enable
Enable
RW
RW
Disable
Disable
Enable
Enable
Type
0
1
PWD
1
1
1
1
1
1
1
1
SMBus Table: Output Stop Control Register
Byte 2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
-
-
-
-
-
-
DIF_1 STOP EN
DIF_0 STOP EN
DIF_3 STOP EN
DIF_2 STOP EN
Name
Control Function
Reserved
Free Run/ Stop Enable
Free Run/ Stop Enable
Reserved
Reserved
Free Run/ Stop Enable
Free Run/ Stop Enable
Reserved
RW
RW
Free-run
Free-run
Stop-able
Stop-able
RW
RW
Free-run
Free-run
Stop-able
Stop-able
Type
0
1
PWD
0
0
0
0
0
0
0
0
IDT
TM
/ICS
TM
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
0839O—12/03/08
5
嵌入式系统
