DATASHEET
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Description
The
ICS9FG104D
is a Frequency Timing Generator that provides 4
differential output pairs that are compliant to the Intel CK410
specification. It also provides support for PCI-Express and SATA.
The part synthesizes several output frequencies from either a
14.31818 Mhz crystal or a 25 MHz crystal. The device can also be
driven by a reference input clock instead of a crystal. It provides
outputs with cycle-to-cycle jitter of less than 50 ps and output-to-
output skew of less than 35 ps. The
ICS9FG104D
also provides a
copy of the reference clock. Frequency selection can be
accomplished via strap pins or SMBus control.
ICS9FG104D
Features/Benefits
•
•
•
•
•
•
Generates common frequencies from 14.318 MHz or
25 MHz
Crystal or reference input
4 - 0.7V current-mode differential output pairs
Supports Serial-ATA at 100 MHz
Two spread spectrum modes: 0 to -0.5 downspread
and +/-0.25% centerspread
Unused inputs may be disabled in either driven or Hi-Z
state for power management.
Key Specifications
•
•
•
•
Output cycle-to-cycle jitter < 50 ps
Output to output skew < 35 ps
+/-300 ppm frequency accuracy on output clocks
+/-50 ppm at any frequency w/spread off
Functional Block Diagram
XIN/CLKIN
OSC
X2
2
R EF OU T
PROGRAMMABLE
SPREAD PLL
STOP
LOGIC
4
DIF(3:0)
SPREAD
SEL14M_25M#
DIF_STOP#
FS(2:0)
SDATA
SCLK
CONTROL
LOGIC
IREF
IDT
®
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
1541C—12/16/10
1
ICS9FG104D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Pin Configuration
XIN/CLKIN
X2
VDD
GND
REFOUT
vFS2
DIF_3
DIF_3#
VDD
GND
DIF_2
DIF_2#
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDDA
GNDA
IREF
vFS0
vFS1
DIF_0
DIF_0#
VDD
GND
DIF_1
DIF_1#
^SEL14M_25M#
vSPREAD
DIF_STOP#
Functionality Table
SEL14M_25M#
FS2 FS1 FS0 OUTPUT(MHz)
(FS3)
0
0
0
0
100.00
0
0
0
1
125.00
0
0
1
0
133.33
0
0
1
1
166.67
0
1
0
0
200.00
0
1
0
1
266.00
0
1
1
0
333.00
0
1
1
1
400.00
1
0
0
0
100.00
1
0
0
1
125.00
1
0
1
0
133.33
1
0
1
1
166.67
1
1
0
0
200.00
1
1
0
1
266.00
1
1
1
0
333.00
1
1
1
1
400.00
^ Pin has internal 120K pull up
v Pin has internal 120K pull down
28-pin SSOP/TSSOP
Power Groups
Pin Number
VDD
GND
3
4
9,21
10,20
28
27
Description
REFOUT, Digital Inputs
DIF Outputs
IREF, Analog VDD, GND for PLL Core
IDT
®
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG104D
1541C—12/16/10
2
ICS9FG104D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Pin Description
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PIN NAME
XIN/CLKIN
X2
VDD
GND
REFOUT
vFS2
DIF_3
DIF_3#
VDD
GND
DIF_2
DIF_2#
SDATA
SCLK
DIF_STOP#
vSPREAD
^SEL14M_25M#
DIF_1#
DIF_1
GND
VDD
DIF_0#
DIF_0
vFS1
vFS0
PIN TYPE
IN
OUT
PWR
PWR
OUT
IN
OUT
OUT
PWR
PWR
OUT
OUT
I/O
IN
IN
IN
IN
OUT
OUT
PWR
PWR
OUT
OUT
IN
IN
DESCRIPTION
Crystal input or Reference Clock input
Crystal output, Nominally 14.318MHz
Power supply, nominal 3.3V
Ground pin.
Reference Clock output
3.3V Frequency select latched input pin with internal 120kohm pull down resistor.
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
Ground pin.
0.7V differential true clock output
0.7V differential Complementary clock output
Data pin for SMBus circuitry, 5V tolerant.
Clock pin of SMBus circuitry, 5V tolerant.
Active low input to stop differential output clocks.
Asynchronous, active high input to enable spread spectrum functionality. This pin
has a 120Kohm pull down resistor.
Select 14.31818 MHz or 25 Mhz input frequency. This pin has an internal 120kohm
pull up resistor.
1 = 14.31818 MHz, 0 = 25 MHz
0.7V differential Complementary clock output
0.7V differential true clock output
Ground pin.
Power supply, nominal 3.3V
0.7V differential Complementary clock output
0.7V differential true clock output
3.3V Frequency select latched input pin with internal 120kohm pull down resistor.
3.3V Frequency select latched input pin with internal 120kohm pull down resistor.
This pin establishes the reference for the differential current-mode output pairs. It
requires a fixed precision resistor to ground. 475ohm is the standard value for
100ohm differential impedance. Other impedances require different values. See
data sheet.
Ground pin for the PLL core.
3.3V power for the PLL core.
26
27
28
IREF
GNDA
VDDA
OUT
PWR
PWR
IDT
®
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
1541C—12/16/10
3
ICS9FG104D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Absolute Max
Symbol
Parameter
VDDxx
3.3V Supply Voltage
Ts
Storage Temperature
Tambient Ambient Operating Temp•(Commerical Grade)
Tambient Ambient Operating Temp•(Industrial Grade)
Tcase
Case Temperature
ESD prot
Input ESD protection•human body model
Min
-65
0
-40
2000
Max
4.6
150
+70
+85
115
Units
V
°
C
°C
°C
°C
V
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= T
A M B IENT
; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
V
IH
V
IL
I
IH
I
IL1
Input Low Current
I
IL2
CONDITIONS
MIN
TYP
MAX
V
DD
+ 0.3
UNITS NOTES
V
V
uA
uA
uA
1
1
1
1
1
1
1
1
1
3
3
1
1
1
1,2
1,2
1,3,4
1,3,4
1
1
3.3 V +/-5%
2
V
SS
- 0.3
3.3 V +/-5%
V
IN
= V
DD
-5
V
IN
= 0 V; Inputs with no pull-
-5
up resistors
V
IN
= 0 V; Inputs with pull-up
resistors
Full Active, C
L
= Full load;
f = 400 MHz
Full Active, C
L
= Full load;
f = 100 MHz
All outputs stopped driven
All outputs stopped Hi-Z
SEL14M_25M# = 0
SEL14M_25M# = 1
Logic Inputs
Output pin capacitance
From V
DD
Power-Up to 1st
clock (Commercial)
From V
DD
Power-Up to 1st
clock (Industrial)
SEL14M_25M# = 0
SEL14M_25M# = 1
DIF output enable after
DIF_Stop# de-assertion
20% to 80% of VDD
-200
125
110
106
48
22.5
25.00
12.886 14.31818
1.5
0.8
5
150
125
120
60
27.5
15.75
7
5
6
1.8
1.8
mA
mA
mA
mA
MHz
MHz
nH
pF
pF
ms
ms
kHz
kHz
I
DD3.3OP
Operating Supply Current
I
DD3.3STOP
Input Frequency
3
Pin Inductance
1
Input/Output
Capacitance
1
Clk Stabilization
1,2
T
STABind
Modulation Frequency
Modulation Frequency
DIF output enable
Input Rise and Fall times
1
F
i
L
pin
C
IN
C
OUT
T
STABcom
f
MOD
f
MOD
t
DIFOE
t
R
/t
F
32.541
32.467
15
5
ns
ns
Guaranteed by design, not 100% tested in production.
2
See timing diagrams for timing requirements.
3
Input frequency should be measured at the REF pin and tuned to 0 PPM to meet
ppm frequency accuracy on PLL outputs.
These values assume 25MHz or 14.31818MHz inputs respectively. Using a higher or lower frequency
will scale these frequencies accordingly. The output frequecy selected by the FS inputs will also scale.
For example, 27MHz input with an FS selection of 100MHz will yield an output frequency of 27/25 x 100 =
108MHz.
IDT
®
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
1541C—12/16/10
4
4
ICS9FG104D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
T
A
= T
A M B IENT
; V
DD
= 3.3 V +/-5%; C
L
=2pF, R
S
=33.2
Ω
, R
P
=49.9
Ω
, I
REF
= 475
Ω
PARAMETER
Output Impedance
Voltage High
Voltage Low
Max Voltage
Min Voltage
Crossing Voltage (abs)
Crossing Voltage (var)
Long Accuracy
SYMBOL
Zo
1
VHigh
VLow
Vovs
Vuds
Vcross(abs)
d-Vcross
ppm
CONDITIONS
V
O
= V
x
Statistical measurement on
single ended signal using
oscilloscope math function.
Measurement on single ended
signal using absolute value.
Crossing variation over all edges
see Tperiod min-max values
400MHz nominal
400MHz spread
333.33MHz nominal
333.33MHz spread
266.66MHz nominal
266.66MHz spread
200MHz nominal
200MHz spread
166.66MHz nominal
166.66MHz spread
133.33MHz nominal
133.33MHz spread
100.00MHz nominal
100.00MHz spread
400MHz nominal/spread
333.33MHz nominal/spread
266.66MHz nominal/spread
200MHz nominal/spread
166.66MHz nominal/spread
133.33MHz nominal/spread
100.00MHz nominal/spread
V
OL
= 0.175V, V
OH
= 0.525V
V
OH
= 0.525V V
OL
= 0.175V
MIN
3000
660
-150
-300
250
850
mV
150
1150
550
140
-300
300
2.49988 2.5000 2.5001
2.4993
2.5133
2.99985 3.0000 3.0002
2.9991
3.016
3.74981 3.7500 3.7502
3.7489
3.77
4.9998 5.0000 5.0003
4.9985
5.0266
5.9997 6.0000 6.0003
5.9982
6.0320
7.4996 7.5000 7.5004
7.4978
5.4000
9.9995 10.0000 10.0005
9.9970
10.0533
2.4143
2.9141
3.6639
4.8735
5.8732
7.3728
9.8720
175
700
175
700
125
125
45
55
35
50
mV
mV
mV
ppm
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
%
ps
ps
1
1
1
1
1
1,2,5
2
2,3
2
2,3
2
2,3
2
2,3
2
2,3
2
2,3
2
2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1
1
1
1
1
1
1
TYP
MAX
UNITS
Ω
NOTES
1
1
Average period
Tperiod
Absolute min period
T
absmin
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
Duty Cycle
Skew, output to output
Jitter, Cycle to cycle
1
2
t
r
t
f
d-t
r
d-t
f
d
t3
t
sk3
t
jcyc-cyc
Measured Differentially
V
T
= 50%
Measured Differentially
Guaranteed by design and characterization, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is tuned to 0
3
Figures are for down spread.
4
This figure is the peak-to-peak phase jitter as defined by PCI-SIG for a PCI Express reference clock. Please visit
http://www.pcisig.com for additional details
5
+/- 50 ppm at any frequency with spread off
IDT
®
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
1541C—12/16/10
5
