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HIGH-SPEED 2.5V

PRELIMINARY

512/256/128K X 18

IDT70T3339/19/99S

SYNCHRONOUS

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

Features:

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed data access

– Commercial: 3.4 (200MHz)/3.6ns (166MHz)/

4.2ns (133MHz)(max.)

– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)

Selectable Pipelined or Flow-Through output mode

Counter enable and repeat features

Dual chip enables allow for depth expansion without

additional logic

Interrupt and Collision Detection Flags

Full synchronous operation on both ports

– 5ns cycle time, 200MHz operation (14Gbps bandwidth)

– Fast 3.4ns clock to data out

– 1.5ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 200MHz

◆

– Data input, address, byte enable and control registers

– Self-timed write allows fast cycle time

Separate byte controls for multiplexed bus and bus

matching compatibility

Dual Cycle Deselect (DCD) for Pipelined Output Mode

2.5V (±100mV) power supply for core

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V

(±100mV) power supply for I/Os and control signals on

each port

Industrial temperature range (-40°C to +85°C) is

available at 166MHz and 133MHz

Available in a 256-pin Ball Grid Array (BGA), a 144-pin Thin

Quad Flatpack (TQFP) and 208-pin fine pitch Ball Grid Array

(fpBGA)

Supports JTAG features compliant with IEEE 1149.1

Due to limited pin count JTAG, Collision Detection and

Interrupt are not supported on the 144-pin TQFP package

Functional Block Diagram

FT/PIPE

1/0

0a 1a

0b 1b

1b 0b

1a 0a

1/0

/PIPE

R/W

1/0

B B

0 1

L L

B B

1 0

R R

1/0

Dout0-8_L

Dout9-17_L

Dout0-8_R

Dout9-17_R

1b 0b 1a 0a

FT/PIPE

0/1

0a 1a 0b

0/1

/PIPE

512/256/128K x 18

MEMORY

ARRAY

I/O

- I/O

17L

Din_L

Din_R

I/O

- I/O

17R

CLK

18L(1)

REPEAT

ADS

CNTEN

18R(1)

CLK

Counter/

Address

Reg.

ADDR_L

ADDR_R

Counter/

Address

Reg.

REPEAT

ADS

CNTEN

TDI

TCK

TMS

TRST

0 L

CE1L

INTERRUPT

COLLISION

DETECTION

LOGIC

0 R

CE1 R

JTAG

TDO

COL

INT

COL

INT

(2)

CONTROL

LOGIC

(2)

5652 drw 01

NOTES:

1. Address A

is a NC for the IDT70T3319. Also, Addresses A

and A

are NC's for the IDT70T3399.

2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and

OPTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode.

NOVEMBER 2003

DSC-5652/3

IDT70T3339/19/99S

High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM

PRELIMINARY

Industrial and Commercial Temperature Ranges

Description:

The IDT70T3339/19/99 is a high-speed 512/256/128k x 18 bit

synchronous Dual-Port RAM. The memory array utilizes Dual-Port

memory cells to allow simultaneous access of any address from both ports.

Registers on control, data, and address inputs provide minimal setup and

hold times. The timing latitude provided by this approach allows systems

to be designed with very short cycle times. With an input data register, the

IDT70T3339/19/99 has been optimized for applications having unidirec-

tional or bidirectional data flow in bursts. An automatic power down feature,

controlled by

and CE

permits the on-chip circuitry of each port to

enter a very low standby power mode.

The IDT70T3339/19/99 can support an operating voltage of either

3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power

supply for the core of the device (V

) is at 2.5V.

6.42

IDT70T3339/19/99S

High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM

PRELIMINARY

Industrial and Commercial Temperature Ranges

Pin Configuration

(3,4,5,6,9)

70T3339/19/99BC

BC-256

(8)

01/13/03

256-Pin BGA

Top View

(9)

A10

A11

A12

A13

A14

A15

A16

TDI

17L

(2)

14L

11L

CNTEN

B10

B11

B12

B13

B14

B15

B16

INT

TDO A

18L

(1)

15L

12L

R/W

REPEAT

C10

C11

C12

C13

C14

C15

C16

COL

I/O

16L

13L

10L

CLK

ADS

D10

D11

D12

D13

OPT

D14

D15

I/O

D16

I/O

PIPE/

DDQL

DDQR

DDQL

DDQR

E10

E11

E12

E13

E14

E15

I/O

E16

I/O

10R

I/O

10L

DDQL

F10

F11

DDQR

F12

F13

F14

I/O

F15

F16

I/O

11L

I/O

11R

DDQL

G10

G11

DDQR

I/O

G12

G13

G14

G15

I/O

G16

I/O

12L

DDQR

H10

H11

H12

DDQL

I/O

H13

H14

H15

H16

I/O

12R

NC V

DDQR

J10

J11

J12

DDQL

J13

J14

J15

I/O

J16

I/O

13L

I/O

14R

I/O

13R

DDQL

K10

K11

DDQR

I/O

K12

K13

K14

K15

K16

I/O

14L

DDQL

L10

L11

L12

DDQR

L13

L14

L15

I/O

L16

I/O

15L

I/O

15R

DDQR

M10

M11

M12

DDQL

I/O

M13

M14

M15

I/O

M16

I/O

16R

I/O

16L

NC V

DDQR

N10

N11

N12

DDQL

I/O

N13

N14

I/O

N15

N16

I/O

17R

PIPE/

DDQR

DDQL

DDQR

DDQL

P10

P11

P12

P13

P14

I/O

P15

P16

COL

I/O

17L

TMS

16R

18R

(1)

13R

10R

CLK

ADS

R10

R11

R12

R13

R14

R15

I/O

R16

INT

TRST

15R

12R

R/W

REPEAT

T10

T11

T12

T13

OPT

T14

T15

T16

TCK

17R

(2)

14R

11R

CNTEN

5652 drw 02d

NOTES:

1. Pin is a NC for IDT70T3319 and IDT70T3399.

2. Pin is a NC for IDT70T3399.

3. All V

pins must be connected to 2.5V power supply.

4. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(2.5V), and 2.5V if OPT pin for that port is

set to V

(0V).

5. All V

pins must be connected to ground supply.

6. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.

7. This package code is used to reference the package diagram.

8. This text does not indicate orientation of the actual part-marking.

9. Pins A15 and T15 will be V

REFL

and V

REFR

respectively for future HSTL device.

6.42

IDT70T3339/19/99S

High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM

PRELIMINARY

Industrial and Commercial Temperature Ranges

Pin Configuration(con't)

(3,4,5,6,9,10)

PL/FT

18L

(1)

17L

(2)

16L

15L

14L

13L

12L

11L

10L

CLK

R/W

ADS

CNTEN

REPEAT

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

01/07/03

DDQR

I/O

10L

I/O

10R

I/O

11L

I/O

11R

DDQL

I/O

12L

I/O

12R

DDQR

DDQL

I/O

13R

I/O

13L

I/O

14R

I/O

14L

DDQR

I/O

15R

I/O

15L

I/O

16R

I/O

16L

I/O

17R

I/O

17L

DDQL

70T3339/19/99DD

DD-144

(7)

144-Pin TQFP

Top View

(8)

108

107

106

105

104

103

102

101

100

OPT

DDQR

I/O

DDQL

I/O

DDQR

DDQL

I/O

DDQR

I/O

DDQL

OPT

5652 drw 02a

NOTES:

1. Pin is a NC for IDT70T3319 and IDT70T3399.

2. Pin is a NC for IDT70T3399.

3. All V

pins must be connected to 2.5V power supply.

4. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(2.5V), and 2.5V if OPT pin for that port is set to V

(0V).

5. All V

pins must be connected to ground supply.

6. Package body is approximately 20mm x 20mm x 1.4mm.

7. This package code is used to reference the package diagram.

8. This text does not indicate orientation of the actual part-marking.

9. Due to limited pin count, JTAG, Collison Detection and Interrupt are not supported in the DD-144 package.

10. Pins 109 and 72 will be V

REFL

and V

REFR

respectively for future HSTL device.

PL/FT

18R

(1)

17R

(2)

16R

15R

14R

13R

12R

11R

10R

CLK

R/W

ADS

CNTEN

REPEAT

6.42

IDT70T3339/19/99S

High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM

PRELIMINARY

Industrial and Commercial Temperature Ranges

Pin Configurations(con't)

(3,4,5,6,9)

01/13/03

I/O

INT

TDO

16L

12L

10 11

CLK

CNTEN

13 14

OPT

16 17

COL

TDI

17L(2)

13L

ADS

DDQR

I/O

DDQL

I/O

DDQR

PIPE/

18L(1)

14L

10L

R/W

I/O

10L

15L

11L

REPEAT

DDQL

I/O

11L

DDQR

I/O

10R

I/O

DDQL

I/O

11R

I/O

DDQR

I/O

12L

DDQL

I/O

DDQR

I/O

12R

70T3339/19/99BF

BF-208

(7)

208-Pin fpBGA

Top View

(8)

I/O

DDQL

DDQR

I/O

14R

I/O

13R

I/O

DDQL

I/O

14L

DDQR

I/O

13L

I/O

DDQL

I/O

15R

I/O

DDQR

I/O

15L

I/O

DDQL

I/O

16R

I/O

16L

DDQR

COL

TRST

16R

12R

CLK

CNTEN

I/O

17R

TCK

17R(2)

13R

ADS

DDQL

I/O

DDQR

I/O

17L

DDQL

TMS

18R(1)

14R

10R

R/W

INT

PIPE/

15R

11R

REPEAT

OPT

I/O

5652 drw 02c

NOTES:

1. Pin is a NC for IDT70T3319 and IDT70T3399.

2. Pin is a NC for IDT70T3399.

3. All V

pins must be connected to 2.5V power supply.

4. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(2.5V), and 2.5V if OPT pin for that port is

set to V

(0V).

5. All V

pins must be connected to ground supply.

6. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.

7. This package code is used to reference the package diagram.

8. This text does not indicate orientation of the actual part-marking.

9. Pins B14 and R14 will be V

REFL

and V

REFR

respectively for future HSTL device.

6.42

参数对比

与IDT70T3399S200BF相近的元器件有：IDT70T3339S166DDI、IDT70T3339S166BFI、IDT70T3399S166BFI、IDT70T3319S166BFI、IDT70T3319S200DD、IDT70T3339S200DD、IDT70T3399S200DD、IDT70T3339S200BF、IDT70T3319S200BF。描述及对比如下：

型号	IDT70T3399S200BF	IDT70T3339S166DDI	IDT70T3339S166BFI	IDT70T3399S166BFI	IDT70T3319S166BFI	IDT70T3319S200DD	IDT70T3339S200DD	IDT70T3399S200DD	IDT70T3339S200BF	IDT70T3319S200BF
描述	Dual-Port SRAM, 128KX18, 10ns, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, FINE PITCH, BGA-208	Dual-Port SRAM, 512KX18, 12ns, CMOS, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, TQFP-144	Dual-Port SRAM, 512KX18, 12ns, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, FINE PITCH, BGA-208	Dual-Port SRAM, 128KX18, 12ns, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, FINE PITCH, BGA-208	Dual-Port SRAM, 256KX18, 12ns, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, FINE PITCH, BGA-208	Dual-Port SRAM, 256KX18, 10ns, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, TQFP-144	Dual-Port SRAM, 512KX18, 10ns, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, TQFP-144	Dual-Port SRAM, 128KX18, 10ns, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, TQFP-144	Dual-Port SRAM, 512KX18, 10ns, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, FINE PITCH, BGA-208	Dual-Port SRAM, 256KX18, 10ns, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, FINE PITCH, BGA-208
是否Rohs认证	不符合	不符合	不符合	不符合	不符合	不符合	不符合	不符合	不符合	不符合
零件包装代码	BGA	QFP	BGA	BGA	BGA	QFP	QFP	QFP	BGA	BGA
包装说明	TFBGA,	20 X 20 MM, 1.40 MM HEIGHT, TQFP-144	TFBGA,	TFBGA,	TFBGA,	20 X 20 MM, 1.40 MM HEIGHT, TQFP-144	20 X 20 MM, 1.40 MM HEIGHT, TQFP-144	20 X 20 MM, 1.40 MM HEIGHT, TQFP-144	TFBGA,	TFBGA,
针数	208	144	208	208	208	144	144	144	208	208
Reach Compliance Code	compliant	not_compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant
ECCN代码	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
最长访问时间	10 ns	12 ns	12 ns	12 ns	12 ns	10 ns	10 ns	10 ns	10 ns	10 ns
其他特性	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 代码	S-PBGA-B208	S-PQFP-G144	S-PBGA-B208	S-PBGA-B208	S-PBGA-B208	S-PQFP-G144	S-PQFP-G144	S-PQFP-G144	S-PBGA-B208	S-PBGA-B208
JESD-609代码	e0	e0	e0	e0	e0	e0	e0	e0	e0	e0
长度	15 mm	20 mm	15 mm	15 mm	15 mm	20 mm	20 mm	20 mm	15 mm	15 mm
内存密度	2359296 bit	9437184 bit	9437184 bit	2359296 bit	4718592 bit	4718592 bit	9437184 bit	2359296 bit	9437184 bit	4718592 bit
内存集成电路类型	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM
内存宽度	18	18	18	18	18	18	18	18	18	18
功能数量	1	1	1	1	1	1	1	1	1	1
端子数量	208	144	208	208	208	144	144	144	208	208
字数	131072 words	524288 words	524288 words	131072 words	262144 words	262144 words	524288 words	131072 words	524288 words	262144 words
字数代码	128000	512000	512000	128000	256000	256000	512000	128000	512000	256000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	70 °C	85 °C	85 °C	85 °C	85 °C	70 °C	70 °C	70 °C	70 °C	70 °C
组织	128KX18	512KX18	512KX18	128KX18	256KX18	256KX18	512KX18	128KX18	512KX18	256KX18
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	TFBGA	LFQFP	TFBGA	TFBGA	TFBGA	LFQFP	LFQFP	LFQFP	TFBGA	TFBGA
封装形状	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
封装形式	GRID ARRAY, THIN PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH
并行/串行	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
峰值回流温度（摄氏度）	225	225	225	225	225	225	225	225	225	225
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	1.2 mm	1.6 mm	1.2 mm	1.2 mm	1.2 mm	1.6 mm	1.6 mm	1.6 mm	1.2 mm	1.2 mm
最大供电电压 (Vsup)	2.6 V	2.6 V	2.6 V	2.6 V	2.6 V	2.6 V	2.6 V	2.6 V	2.6 V	2.6 V
最小供电电压 (Vsup)	2.4 V	2.4 V	2.4 V	2.4 V	2.4 V	2.4 V	2.4 V	2.4 V	2.4 V	2.4 V
标称供电电压 (Vsup)	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
表面贴装	YES	YES	YES	YES	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
端子面层	Tin/Lead (Sn/Pb)	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
端子形式	BALL	GULL WING	BALL	BALL	BALL	GULL WING	GULL WING	GULL WING	BALL	BALL
端子节距	0.8 mm	0.5 mm	0.8 mm	0.8 mm	0.8 mm	0.5 mm	0.5 mm	0.5 mm	0.8 mm	0.8 mm
端子位置	BOTTOM	QUAD	BOTTOM	BOTTOM	BOTTOM	QUAD	QUAD	QUAD	BOTTOM	BOTTOM
处于峰值回流温度下的最长时间	20	30	20	20	20	20	20	20	20	20
宽度	15 mm	20 mm	15 mm	15 mm	15 mm	20 mm	20 mm	20 mm	15 mm	15 mm
是否无铅	含铅	-	含铅	含铅	含铅	含铅	含铅	含铅	含铅	含铅
厂商名称	IDT (Integrated Device Technology)	-	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
湿度敏感等级	3	4	3	3	3	-	-	-	3	3