For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
DECEMBER 1996
DSC-2748/7
5.02
1
IDT72413
CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
OE
HF
IR
SI
D
0
D
1
D
2
D
3
D
4
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Vcc
AF/E
SO
OR
Q
0
Q
1
Q
2
Q
3
Q
4
MR
2748 drw 02
Rating
Terminal Voltage
with Respect
to GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
DC Output
Current
Commercial
-0.5 to +7.0
Military
-0.5 to +7.0
Unit
V
V
TERM
P20-1,
C20-1,
&
SO20-2
17
16
15
14
13
12
11
T
A
T
BIAS
T
STG
I
OUT
0 to +70
-55 to +125
-55 to +125
50
-55 to +125
-65 to +135
-65 to +150
50
°C
°C
°C
mA
DIP/SOIC
TOP VIEW
NOTE:
2748 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
5
7
Unit
pF
pF
2748 tbl 02
NOTE:
1. This parameter is sampled and not 100% tested.
2. Characterized values, not currently listed.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
CC
GND
V
IH
V
IL(1)
Parameter
Military Supply
Voltage
Commercial Supply
Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Min.
4.5
4.5
0
2.0
—
Typ.
5.0
5.0
0
—
—
Max. Unit
5.5
5.5
0
—
0.8
V
V
V
V
V
2748 tbl 03
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
5.02
2
IDT72413
CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5.0V
±
10%, T
A
= 0°C to +70°C; Military: V
CC
= 5.0V
±
10%, T
A
= –55°C to +125°C)
Symbol
I
IL
I
IH
V
OL
Parameter
Low-Level Input Current
High-Level Input Current
Low-Level Output Current
Test Conditions
V
CC
= Max., GND
≤
V
I
≤
V
CC
V
CC
= Max., GND
≤
V
I
≤
V
CC
V
CC
= Min. I
OL
(Q
0-4
) Mil.
I
OL
(IR, OR)
(1)
I
OL
(HF, AF/E)
V
OH
High-Level Output Current
V
CC
= Min. I
OH
(Q
0-4
)
I
OH
(IR, OR)
I
OH
(HF, AF/E)
I
OS(2)
I
HZ
I
LZ
I
CC(3)
Supply Current
Output Short-Circuit Current
Off-State Output Current
V
CC
= Max. V
O
= 0V
V
CC
= Max. V
O
= 2.4V
V
CC
= Max. V
O
= 0.4V
V
CC
= Max., OE=HIGH Mil.
Inputs LOW, f=25MHz Com'l.
12mA
8mA
8mA
–4mA
–4mA
–4mA
-20
—
-20
—
—
-110
20
—
70
60
mA
mA
µA
2.4
—
V
Com'l. 24mA
Min.
-10
—
—
Max.
—
10
0.4
Unit
µA
µA
V
NOTES:
2748 tbl 04
1. Care should be taken to minimize as much as possible the DC and capactive load on IR and OR when operating at frequencies above 25mHz.
2. Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second. Guaranteed by design, but not
currently tested.
3. For frequencies greater than 25MHz, I
CC
= 60mA + (1.5mA x [f - 25MHz]) commercial and I
CC
= 70mA + (1.5mA x [f - 25MHz]) military.
OPERATING CONDITIONS
(Commercial: V
CC
= 5.0V
±
10%, T
A
= 0°C to +70°C; Military: V
CC
= 5.0V
±
10%, T
A
= –55°C to +125°C)
Commercial
Military & Commercial
Military & Commercial
Symbol
t
SIH
t
SIL
t
IDS
t
IDH
t
SOH
t
SOL
t
MRW
t
MRS
(1)
(1)
(1)
Parameters
Shift in HIGH Time
Shift in LOW TIme
Input Data Set-up
Input Data Hold Time
Shift Out HIGH Time
Shift Out LOW Time
Master Reset Pulse
Master Reset Pulse to SI
Figure
2
2
2
2
5
5
8
8
IDT72413L45
Min.
Max.
9
11
0
13
9
11
20
20
—
—
—
—
—
—
—
—
IDT72413L35
Min.
Max.
9
17
0
15
9
17
30
35
—
—
—
—
—
—
—
—
IDT72413L25
Min.
Max.
16
20
0
25
16
20
35
35
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
NOTE:
2748 tbl 05
1. Since the FIFO is a very high-speed device, care must be excercised in the design of the hardware and timing utilized within the design. Device grounding
and decoupling are crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor
supply decoupling and grounding. A monolithic ceramic capacitor of 0.1µF directly between VCC and GND with very short lead length is recommended.
5.02
3
IDT72413
CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5.0V
±
10%, T
A
= 0°C to +70°C; Military: V
CC
= 5.0V
±
10%, T
A
= –55°C to +125°C)
Commercial
Symbol
f
IN
t
IRL
(1)
Mil. & Com'l
IDT72413L35
Min.
Max.
—
—
—
—
—
—
5
—
—
—
—
—
—
—
—
5
5
—
—
—
—
—
—
—
—
—
—
—
35
18
20
35
18
20
—
20
28
28
28
28
25
28
28
—
—
5
28
28
28
28
28
28
12
12
15
15
Mil. & Com'l
IDT72413L25
Min.
Max.
—
—
—
—
—
—
5
—
—
—
—
—
—
—
—
5
5
—
—
—
—
—
—
—
—
—
—
—
25
28
25
25
28
25
—
20
40
30
30
30
35
40
40
—
—
7
40
40
40
40
40
40
15
15
20
20
ns
Unit
MHz
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameters
Shift In Rate
Shift In
↑
to Input Ready LOW
Shift In
↓
to Input Ready HIGH
Shift Out Rate
Shift Out
↓
to Output Ready LOW
Shift Out
↓
to Output Ready HIGH
Output Data Hold Previous Word
Output Data Shift Next Word
Data Throughput or "Fall-Through"
Master Reset
↓
to Output Ready LOW
Master Reset
↑
to Input Ready HIGH
Master Reset
↓
to Input Ready LOW
Master Reset
↓
to Outputs LOW
Master Reset
↓
to Half-Full Flag
Master Reset
↓
to AF/E Flag
Input Ready Pulse HIGH
Ouput Ready Pulse HIGH
Output Ready
↑
HIGH to Valid Data
Shift Out
↑
to AF/E HIGH
Shift In
↑
to AF/E
Shift Out
↑
to AF/E LOW
Shift In
↑
to AF/E HIGH
Shift In
↑
to HF HIGH
Shif Out
↑
to HF LOW
Output Disable Delay
Figure
2
2
2
5
5
5
5
5
4, 7
8
8
8
8
8
8
4
7
5
9
9
10
10
11
11
12
12
IDT72413L45
Min.
Max.
—
—
—
—
—
—
5
—
—
—
—
—
—
—
—
5
5
—
—
—
—
—
—
—
—
—
—
—
45
18
18
45
18
19
—
19
25
25
25
25
20
25
25
—
—
5
28
28
28
28
28
28
12
12
15
15
t
IRH(1)
f
OUT
t
ORL(1)
t
ORH(1)
t
ODH(1)
t
ODS
t
PT
t
MRORL
t
MRIRH
(3)
t
MRIRL(2)
t
MRQ
t
MRHF
t
MRAFE
t
IPH(3)
t
OPH(3)
t
ORD(3)
t
AEH
t
AEL
t
AFL
t
AFH
t
HFH
t
HFL
t
PHZ(3)
t
PLZ(3)
t
PLZ(3)
t
PHZ(3)
Output Enable Delay
12
12
NOTES:
2748 tbl 06
1. Since the FIFO is a very high-speed device, care must be taken in the design of the hardware and the timing utilized within the design. Device grounding
and decoupling are crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor
supply decoupling and grounding. A monolithic ceramic capacitor of 0.1µF directly between VCC and GND with very short lead length is recommended.
2. If the FIFO is full, (IR = HIGH), MR
↓
forces IR to go LOW, and MR
↑
causes IR to go HIGH.
3. Guaranteed by design but not currently tested.
5.02
4
IDT72413
CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1
2748 tbl 07
STANDARD TEST LOAD
5V
R1
OUTPUT
R2
TEST POINT
30pF*
DESIGN TEST LOAD
5V
2KΩ
30pF*
or equivalent
circuit
*Including scope and jig
2748 drw 03
RESISTOR VALUES FOR
STANDARD TEST LOAD
I
OL
24mA
12mA
8mA
R1
200Ω
390Ω
600Ω
Figure 1. Output Load
R2
300Ω
760Ω
1200Ω
2748 tbl 08
FUNCTIONAL DESCRIPTION:
The IDT72413, 65 x 5 FIFO is designed using a dual-port
RAM architecture as opposed to the traditional shift register
approach. This FIFO architecture has a write pointer, a read
pointer and control logic, which allow simultaneous read and
write operations. The write pointer is incremented by the
falling edge of the Shift In (Sl) control; the read pointer is
incremented by the falling edge of the Shift Out (SO). The
Input Ready (IR) signals when the FIFO has an available
memory location; Output Ready (OR) signals when there is
valid data on the output. Output Enable (OE) provides the
capability of three-stating the FIFO outputs.
DATA OUTPUT
Data is shifted out on the HIGH-to-LOW transition of Shift
Out (SO). This causes the internal read pointer to be ad-
vanced to the next word location. If data is present, valid data
will appear on the outputs and Output Ready (OR) will go
HIGH. If data is not present, Output Ready will stay LOW
indicating the FIFO is empty. The last valid word read from the
FIFO will remain at the FlFOs output when it is empty. When
the FIFO is not empty Output Ready (OR) goes LOW on the
LOW-to-HlGH transition of Shift Out.
FALL-THROUGH MODE
The FIFO operates in a Fall-Through Mode when data gets
shifted into an empty FIFO. After the fall-through delay the
data propagates to the output. When the data reaches the
output, the Output Ready (OR) goes HIGH.
A Fall-Through Mode also occurs when the FIFO is
completely full. When data is shifted out of the full FIFO a
location is available for new data. After a fall-through delay,
the lnput Ready goes HlGH. If Shift In is HIGH, the new data
can be written to the FIFO. The fall-through delay of a RAM-
based FIFO (one clock cycle) is far less than the delay of a
Shift register-based FIFO.
FIFO RESET
The FIFO must be reset upon power up using the Master
Reset (MR) signal. This causes the FIFO to enter an empty
state signified by Output Ready (OR) being LOW and Input
Ready (IR) being HIGH. In this state, the data outputs (Q
0-4
)
will be LOW.
DATA INPUT
Data is shifted in on the LOW-to-HIGH transition of Shift In
(Sl). This loads input data into the first word location of the
FIFO and causes the lnput Ready to go LOW. On the HlGH-
to-LOW transition of Shift In, the write pointer is moved to the
next word position and Input Ready (lR) goes HlGH indicating
the readiness to accept new data. If the FIFO is full, Input
Ready will remain LOW until a word of data is shifted out.
刚外网曝光了一组索尼Xperia 2谍照，该机新机遭提前曝光，据外媒称该机本该在今年下半年的 IFA 2019上亮相的。 据悉，这次索尼Xperia 2消息泄密是由@onleaks x cashkaro提供的，他们向外媒展示了新机谍照及一段视频。视频显示，索尼Xperia 2后置三摄已从背面中央移到左侧，闪光灯就在其正上方。 同时，秉承了索尼一贯的影像基因，或搭载引以为傲的C...[详细]
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