2.5V MULTI-QUEUE FIFO (4 QUEUES)
36 BIT WIDE CONFIGURATION
589,824 bits, 1,179,648 bits and
2,359,296 bits
ADVANCE INFORMATION
IDT72T51236
IDT72T51246
IDT72T51256
FEATURES:
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Choose from among the following memory density options:
IDT72T51236
Total Available Memory = 589,824 bits
IDT72T51246
Total Available Memory = 1,179,648 bits
IDT72T51256
Total Available Memory = 2,359,296 bits
Configurable from 1 to 4 Queues
Queues may be configured at master reset from the pool of
Total Available Memory in blocks of 256 x 36
Independent Read and Write access per queue
User selectable I/O: 2.5V LVTTL, 1.5V HSTL, 1.8V eHSTL
User programmable via serial port
Default Multi-Queue device configurations
-IDT72T51236: 4,096 x 36 x 4Q
-IDT72T51246: 8,192 x 36 x 4Q
-IDT72T51256: 16,384 x 36 x 4Q
100% Bus Utilization, Read and Write on every clock cycle
200 MHz High speed operation (5ns cycle time)
3.6ns access time
Echo Read Enable & Echo Read Clock Outputs
Individual, Active queue flags (OV,
FF, PAE, PAF, PR)
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4 bit parallel flag status on both read and write ports
Provides continuous
PAE
and
PAF
status of up to 4 Queues
Global Bus Matching - (All Queues have same Input Bus Width
and Output Bus Width)
User Selectable Bus Matching Options:
- x36in to x36out
- x18in to x36out
- x9in to x36out
- x36in to x18out
- x36in to x9out
FWFT mode of operation on read port
Packet Ready mode of operation
Partial Reset, clears data in single Queue
Expansion of up to 8 Multi-Queue devices in parallel is available
Power Down Input provides additional power savings in HSTL
and eHSTL modes.
JTAG Functionality (Boundary Scan)
Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm
HIGH Performance submicron CMOS technology
Industrial temperature range (-40°C to +85°C) is available
DATA PATH FLOW DIAGRAM
MULTI-QUEUE FIFO
WADEN
FSTR
WRADD
WEN
WCLK
5
READ CONTROL
RADEN
ESTR
RDADD
6
WRITE CONTROL
Q0
REN
RCLK
EREN
ERCLK
OE
x9, x18, x36
DATA IN
FF
PAF
PAFn
Din
Qout
x9, x18, x36
DATA OUT
READ FLAGS
OV
PR
PAE
PAEn
4
WRITE FLAGS
Qmax
4
PRn
6116 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
©2001
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
OCTOBER 2, 2001
DSC-6116/-
IDT72T51236/72T51246/72T51256 2.5V, MULTI-QUEUE FIFO (4 QUEUES)
36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INUSTRIAL
TEMPERATURE RANGES
DESCRIPTION:
The IDT72T51236/72T51246/72T51256 Multi-Queue FIFO device is a
single chip within which anywhere between 1 and 4 discrete FIFO queues can
be setup. All queues within the device have a common data input bus, (write
port) and a common data output bus, (read port). Data written into the write
port is directed to a respective queue via an internal de-multiplex operation,
addressed by the user. Data read from the read port is accessed from a
respective queue via an internal multiplex operation, addressed by the user.
Data writes and reads can be performed at high speeds up to 200MHz, with
access times of 3.6ns. Data write and read operations are totally independent
of each other, a queue maybe selected on the write port and a different queue
on the read port or both ports may select the same queue simultaneously.
The device provides Full flag and Output Valid flag status for the queue
selected for write and read operations respectively. Also a Programmable
Almost Full and Programmable Almost Empty flag for each queue is provided.
Two 4 bit programmable flag busses are available, providing status of all
queues, including queues not selected for write or read operations, these flag
busses provide an individual flag per queue.
Bus Matching is available on this device, either port can be 9 bits, 18 bits
or 36 bits wide provided that at least one port is 36 bits wide. When Bus Matching
is used the device ensures the logical transfer of data throughput in a Little
Endian manner.
A packet ready mode of operation is also provided when the device is
configured for 36 bit input and 36 bit output port sizes. The Packet Ready mode
provides the user with a flag output indicating when at least one (or more)
packets of data within a queue is available for reading. The Packet Ready
provides the user with a means by which to mark the start and end of packets
of data being passed through the FIFO queues. The Multi-Queue device then
provides the user with an internally generated packet ready status per queue.
The user has full flexibility configuring queues within the device, being able
to program the total number of queues between 1 and 4, the individual queue
depths being independent of each other. The programmable flag positions are
also user programmable. All programming is done via a dedicated serial port.
If the user does not wish to program the Multi-Queue device, a default option is
available that configures the device in a predetermined manner.
Both Master Reset and Partial Reset pins are provided on this device. A Master
Reset latches in all configuration setup pins and must be performed before
programming of the device can take place. A Partial Reset will reset the read and
write pointers of an individual FIFO queue, provided that the queue is selected
on both the write port and read port at the time of partial reset.
Echo Read Enable,
EREN
and Echo Read Clock, ERCLK outputs are
provided. These are outputs from the read port of the FIFO that are required for
high speed data communication, to provide tighter synchronization between the
data being transmitted from the Qn outputs and the data being received by the
input device. Data read from the read port is available on the output bus with
respect to
EREN
and ERCLK, this is very useful when data is being read at high
speed.
The Multi-Queue FIFO has the capability of operating its IO in either 2.5V
LVTTL, 1.5V HSTL or 1.8V eHSTL mode. The type of IO is selected via the
IOSEL input. The core supply voltage (V
CC
) to the Multi-Queue is always 2.5V,
however the output levels can be set independently via a separate supply, V
DDQ
.
The devices also provide additional power savings via a Power Down Input.
This input disables the write port data inputs when no write operations are
required.
A JTAG test port is provided, here the Multi-Queue FIFO has a fully functional
Boundary Scan feature, compliant with IEEE 1449.1 Standard Test Access Port
and Boundary Scan Architecture.
See Figure 1,
Multi-Queue FIFO Block Diagram
for an outline of the functional
blocks within the device.
2
IDT72T51236/72T51246/72T51256 2.5V, MULTI-QUEUE FIFO (4 QUEUES)
36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
Din
x9, x18, x36
D0 - D35
WCLK
WEN
INPUT
DEMUX
JTAG
Logic
WRADD
WADEN
2
D35 = TEOP
D34 = TSOP
COMMERCIAL AND INUSTRIAL
TEMPERATURE RANGES
TMS
TDI
TDO
TCK
TRST
5
Write Control
Logic
Write Pointers
Packet Mode
Logic
PR
4
PRn/PAEn
FSTR
PAFn
FSYNC
FXO
FXI
FF
PAF
SI
SO
SCLK
SENI
SENO
FM
IW
OW
BM
MAST
PKT
ID0
ID1
ID2
DF
DFM
PRS
MRS
4
PAF
General Flag
Monitor
Upto 4
FIFO
Queues
Active Q
Flags
0.5 Mbit
1.1 Mbit
2.3 Mbit
Dual Port
Memory
Active Q
Flags
OV
PAE
Serial
Multi-Queue
Programming
PAE
General Flag
Monitor
ESTR
ESYNC
EXI
EXO
Read Pointers
Reset
Logic
6
Read Control
Logic
RDADD
RADEN
NULL-Q
REN
Device ID
3 Bit
PAE/ PAF
Offset
OUTPUT
REGISTER
RCLK
OUTPUT
MUX
2
Q35 = REOP
Q34 = RSOP
EREN
ERCLK
6116 drw02
IOSEL
Vref
PD
IO Level Control
&
Power Down
OE
Q0 - Q35
Qout x9, x18, x36
Figure 1. Multi-Queue Block Diagram
3
IDT72T51236/72T51246/72T51256 2.5V, MULTI-QUEUE FIFO (4 QUEUES)
36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INUSTRIAL
TEMPERATURE RANGES
PIN CONFIGURATION
A1 BALL PAD CORNER
A
D14
D13
D12
D10
D7
D4
D1
TCK
TDO
ID1
Q3
Q6
Q9
Q12
Q14
Q15
B
D15
D16
D11
D9
D6
D3
D0
TMS
TDI
ID0
Q2
Q5
Q8
Q11
Q13
Q19
C
D17
D18
D19
D8
D5
D2
TRST
IOSEL
ID2
Q0
Q1
Q4
Q7
Q10
Q17
Q18
D
D20
D21
D22
E
D23
D24
D25
F
D26
D27
D28
G
D29
D30
D31
H
D32
D33
D34
J
GND
Null Q
D35
K
PD
GND
VREF
L
SI
DFM
DF
M
SENO
SENI
N
WRADD1 WRADD0
SCLK
Y
R
A
IN
IM
L
E
R
P
VDDQ
VDDQ
VDD
VDD
GND
GND
VDD
VDD
VDDQ
VDDQ
Q24
Q23
VDDQ
VDD
GND
GND
GND
GND
GND
GND
VDD
VDDQ
Q27
Q26
VDD
VDD
GND
GND
GND
GND
GND
GND
VDD
VDD
Q30
Q29
VDD
GND
GND
GND
GND
GND
GND
GND
GND
VDD
Q33
Q32
VDD
GND
GND
GND
GND
GND
GND
GND
GND
VDD
PKT
Q35
VDD
VDD
GND
GND
GND
GND
GND
GND
VDD
VDD
GND
VDDQ
VDD
GND
GND
GND
GND
GND
GND
VDD
VDDQ
BM
IW
SO
VDDQ
VDDQ
VDD
VDD
GND
GND
VDD
VDD
VDDQ
VDDQ
OE
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
RDADD2
GND
WADEN
PAF3
DNC
DNC
FF
OV
PAE
DNC
DNC
PAE3
FSTR
PAF2
DNC
DNC
PAF
PR
ERCLK
EREN
DNC
PAE2
RADEN
ESTR
PAF0
PAF1
WEN
WCLK
PRS
MRS
RCLK
REN
DNC
PAE1
PAE0
EXO
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
Q16
Q21
Q20
Q22
Q25
Q28
Q31
Q34
MASTER
FM
OW
RDADD0 RDADD1
GND
P
GND
GND
WRADD2
RDADD5 RDADD6 RDADD7
R
WRADD6 WRADD5
FSYNC
ESYNC
T
WRADD7
FXI
FXO
EXI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
6116 drw03
PBGA (BB256-1, order code: BB)
TOP VIEW
NOTE:
1. DNC - Do Not Connect.
4
IDT72T51236/72T51246/72T51256 2.5V, MULTI-QUEUE FIFO (4 QUEUES)
36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INUSTRIAL
TEMPERATURE RANGES
DETAILED DESCRIPTION
MULTI-QUEUE STRUCTURE
The IDT Multi-Queue FIFO has a single data input port and single data output
port with up to 4 FIFO queues in parallel buffering between the two ports. The
user can setup between 1 and 4 FIFO Queues within the device. These queues
can be configured to utilize the total available memory, providing the user with
full flexibility and ability to configure the queues to be various depths, indepen-
dent of one another.
MEMORY ORGANIZATION/ ALLOCATION
The memory is organized into what is known as “blocks”, each block being
256 x36 bits. When the user is configuring the number of queues and individual
queue sizes the user must allocate the memory to respective queues, in units
of blocks, that is, a single queue can be made up from 0 to m blocks, where m
is the total number of blocks available within a device. Also the total size of any
given queue must be in increments of 256 x36. For the IDT72T51236/
72T51246 and IDT72T51256 the Total Available Memory is 64, 128 and 256
blocks respectively (a block being 256 x36). Queues can be built from these
blocks to make any size queue desired and any number of queues desired.
BUS WIDTHS
The input port is common to all FIFO queues within the device, as is the output
port. The device provides the user with Bus Matching options such that the input
port and output port can be either x9, x18 or x36 bits wide provided that at least
one of the ports is x36 bits wide, the read and write port widths being set
independently of one another. Because the ports are common to all queues the
width of the queues is not individually set, so that the input width of all queues
are equal and the output width of all queues are equal.
WRITING TO & READING FROM THE MULTI-QUEUE
Data being written into the device via the input port is directed to a discrete
FIFO queue via the write queue select address inputs. Conversely, data being
read from the device read port is read from a queue selected via the read queue
select address inputs. Data can be simultaneously written into and read from the
same FIFO queue or different FIFO queues. Once a queue is selected for data
writes or reads, the writing and reading operation is performed in the same
manner as conventional IDT synchronous FIFO’s, utilizing clocks and enables,
there is a single clock and enable per port. When a specific queue is addressed
on the write port, data placed on the data inputs is written to that queue
sequentially based on the rising edge of a write clock provided setup and hold
times are met. Conversely, data is read on to the output port after an access time
from a rising edge on a read clock.
The operation of the write port is comparable to the function of a conventional
FIFO operating in standard IDT mode. Write operations can be performed on
the write port provided that the queue currently selected is not full, a full flag output
provides status of the selected queue. The operation of the read port is
comparable to the function of a conventional FIFO operating in FWFT mode.
When a FIFO queue is selected on the output port, the next word in that queue
will automatically fall through to the output register. All subsequent words from
that queue require an enabled read cycle. Data cannot be read from a selected
queue if that queue is empty, the read port provides an Output Valid flag indicating
when data read out is valid. If the user switches to a queue that is empty, the
last word from the previous queue will remain on the output register.
As mentioned, the write port has a full flag, providing full status of the selected
queue. Along with the full flag a dedicated almost full flag is provided, this almost
full flag is similar to the almost full flag of a conventional IDT FIFO. The device
5
provides a user programmable almost full flag for all 4 FIFO queues and when
a respective queue is selected on the write port, the almost full flag provides status
for that queue. Conversely, the read port has an output valid flag, providing
status of the data being read from the queue selected on the read port. As well
as the output valid flag the device provides a dedicated almost empty flag. This
almost empty flag is similar to the almost empty flag of a conventional IDT FIFO.
The device provides a user programmable almost empty flag for all 4 FIFO
queues and when a respective queue is selected on the read port, the almost
empty flag provides status for that queue.
PROGRAMMABLE FLAG BUSSES
In addition to these dedicated flags, full & almost full on the write port and output
valid & almost empty on the read port, there are two flag status busses. An almost
full flag status bus is provided, this bus is 4 bits wide. Also, an almost empty flag
status bus is provided, again this bus is 4 bits wide. The purpose of these flag
busses is to provide the user with a means by which to monitor the data levels
within FIFO queues that may not be selected on the write or read port. As
mentioned, the device provides almost full and almost empty registers (program-
mable by the user) for each of the 4 FIFO queues in the device.
The 4 bit
PAEn
and 4 bit
PAFn
busses provide a discrete status of the Almost
Empty and Almost Full conditions of all 4 queue's. If the device is programmed
for less than 4 queue's, then there will be a corresponding number of active
outputs on the
PAEn
and
PAFn
busses.
The flag busses can provide a continuous status of all queues. If devices are
connected in expansion mode the individual flag busses can be left in a discrete
form, providing constant status of all queues, or the busses of individual devices
can be connected together to produce a single bus of 4 bits. The device can
then operate in a "Polled" or "Direct" mode.
When operating in polled mode the flag bus provides status of each device
sequentially, that is, on each rising edge of a clock the flag bus is updated to show
the status of each device in order. The rising edge of the write clock will update
the Almost Full bus and a rising edge on the read clock will update the Almost
Empty bus.
When operating in direct mode the device driving the flag bus is selected by
the user. The user addresses the device that will take control of a respective
flag bus, these
PAFn
and
PAEn
flag busses operating independently of one
another. Addressing of the Almost Full flag bus is done via the write port and
addressing of the Almost Empty flag bus is done via the read port.
PACKET READY
The 36 bit Multi-Queue FIFO also offers a ”Packet Ready” mode of operation,
this is user selectable and requires that the device be configured with both write
and read ports as 36 bits wide. The packet mode of operation provides
monitoring of “user marked” locations, when the user is writing data into a FIFO
queue a word being written in can be marked as a “Start of Packet” or “End of
Packet”. Internally as words are being written into the device with markers
attached, the device monitors these markers and provides a packet ready status
flag, which indicates when at least one full packet is available in a queue. The
read port therefore includes an additional status flag, “Packet Ready”, this flag
providing packet ready status for the queue currently selected on the read port
for read operations, indicating when at least one (or more) packets of data are
available to be read. When in packet ready mode the almost empty flag status
bus no longer provides almost empty status for individual quadrants, but instead
provides packet ready flag status for individual quadrants. (A packet is regarded
as any number of words written between a start of packet and end of packet
marker, packet sizes are user defined and sizes are not controlled or limited by
the device).
ADI参考电路
