3.3 VOLT MULTIMEDIA FIFO
256 x 8, 512 x 8,
1,024 x 8, 2,048 x 8,
and 4,096 x 8
IDT72V10081, IDT72V11081
IDT72V12081, IDT72V13081
IDT72V14081
FEATURES
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DESCRIPTION
The IDT72V10081/72V11081/72V12081/72V13081/72V14081 devices
are low-power First-In, First-Out (FIFO) memories with clocked read and write
controls. These devices have a 256, 512, 1,024, 2,048 and 4,096 x 8-bit
memory array, respectively. These FIFOs are applicable for a wide variety of
data buffering needs such as graphics and interprocessor communication.
These FIFOs have 8-bit input and output ports. The input port is
controlled by a free-running clock (WCLK) and Write Enable pin (WEN).
Data is written into the Multimedia FIFO on every rising clock edge when
the Write Enable pin is asserted. The output port is controlled by another
clock pin (RCLK) and Read Enable pin (REN). The Read Clock can be
tied to the Write Clock for single clock operation or the two clocks can run
asynchronous of one another for dual-clock operation. An Output Enable
pin (OE) is provided on the read port for three-state control of the output.
The Multimedia FIFOs have two fixed flags, Empty (EF) and Full (FF).
These FIFOs are fabricated using IDT's submicron CMOS technology.
256 x 8-bit organization array (IDT72V10081)
512 x 8-bit organization array (IDT72V11081)
1,024 x 8-bit organization array (IDT72V12081)
2,048 x 8-bit organization array (IDT72V13081)
4,096 x 8-bit organization array (IDT72V14081)
15 ns read/write cycle time
5V input tolerant
Independent Read and Write clocks
Empty and Full Flags signal FIFO status
Output Enable puts output data bus in high-impedance state
Available in 32-pin plastic Thin Quad FlatPack (TQFP)
Industrial temperature range (–40°C to +85°C)
°
°
FUNCTIONAL BLOCK DIAGRAM
WCLK
WEN
WRITE
CONTROL
READ
CONTROL
RCLK
REN
FIFO ARRAY
D
0
- D
7
Data In
x8
OE
Q
0
- Q
7
Data Out
x8
RESET LOGIC
FLAG OUTPUTS
RS
EF
FF
6161 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGES
1
2003
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
NOVEMBER 2003
DSC-6161/2
IDT72V10081/11081/12081/13081/14081 3.3V MULTIMEDIA FIFO
256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
GND
INDEX
32 31 30 29 28 27 26 25
D
6
D
7
DNC
(1)
DNC
(1)
GND
R
EN
RCLK
GND
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
6161 drw02
RS
D
5
D
4
D
3
D
2
D
1
D
0
24
23
22
21
20
19
18
17
WEN
WCLK
V
CC
V
CC
Q
0
Q
1
Q
2
Q
3
FF
Q
7
Q
6
Q
5
Q
4
NOTE:
1. DNC = Do Not Connect.
TQFP (PR32-1, order code: PF)
TOP VIEW
PIN DESCRIPTIONS
Symbol
D
0
-D
7
EF
FF
OE
Name
Data Inputs
Empty Flag
Full Flag
Output Enable
Data Outputs
Read Clock
Read Enable
Reset
Write Clock
Write Enable
Power
Ground
I/O
I
O
O
I
O
I
I
I
I
I
I
I
DNC
(1)
OE
EF
Description
Data inputs for a 8-bit bus.
When
EF
is LOW, the FIFO is empty and further data reads from the output are inhibited. When
EF
is
HIGH, the FIFO is not empty.
EF
is synchronized to RCLK.
When
FF
is LOW, the FIFO is full and further data writes into the input are inhibited. When
FF
is HIGH, the FIFO
is not full.
FF
is synchronized to WCLK.
When
OE
is LOW, the data output bus is active. If
OE
is HIGH, the output data bus will be in a high-impedance
state.
Data outputs for a 8-bit bus.
Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when
REN
is asserted.
When
REN
is LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK.
Data will not be read from the FIFO if the
EF
is LOW.
When
RS
is set LOW, internal read and write pointers are set to the first location of the RAM array,
FF
goes HIGH, and
EF
goes LOW. A Reset is required before an initial Write after power-up.
Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when the Write Enable is asserted.
When
WEN
is LOW, data is written into the FIFO on every LOW-to-HIGH transition WCLK. Data
will not be written into the FIFO if the
FF
is LOW.
3.3V volt power supply.
Ground pin.
Q
0
-Q
7
RCLK
REN
RS
WCLK
WEN
V
CC
GND
2
IDT72V10081/11081/12081/13081/14081 3.3V MULTIMEDIA FIFO
256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
(2)
T
STG
I
OUT
Rating
Terminal Voltage with
Respect to GND
Storage Temperature
DC Output Current
Industrial
–0.5 to +5
–55 to +125
–50 to +50
Unit
V
°C
mA
RECOMMENDED OPERATING
CONDITIONS
Symbol
V
CC
GND
V
IH
V
IL
T
A
Parameter
Supply Voltage Industrial
Supply Voltage
Input High Voltage Industrial
Input Low Voltage Industrial
Operating Temperature
Industrial
Min.
3.0
0
2.0
-0.5
-40
Typ.
3.3
0
—
—
—
Max. Unit
3.6
0
5.5
0.8
85
V
V
V
V
°C
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of the specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
CC
terminal only.
DC ELECTRICAL CHARACTERISTICS
(Industrial: V
CC
= 3.3V ± 0.3V, T
A
= -40°C to +85°C)
IDT72V10081
IDT72V11081
IDT72V12081
IDT72V13081
IDT72V14081
Industrial
t
CLK
= 15 ns
Symbol
I
LI
(1)
I
LO
(2)
V
OH
V
OL
I
CC1
(3,4,5)
I
CC2
(3,6)
Parameter
Input Leakage Current (Any Input)
Output Leakage Current
Output Logic “1” Voltage, I
OH
= –2mA
Output Logic “0” Voltage, I
OL
= 8mA
Active Power Supply Current
Standby Current
Min.
–1
–10
2.4
—
—
—
Typ.
—
—
—
—
—
—
Max.
1
10
—
0.4
20
5
Unit
µA
µA
V
V
mA
mA
NOTES:
1. Measurements with 0.4
≤
VIN
≤
VCC.
2.
OE
≥
V
IH,
0.4
≤
V
OUT
≤
V
CC
.
3. Tested with outputs disabled (I
OUT
= 0).
4. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
5. Typical I
CC1
= 0.17 + 0.48*f
S
+ 0.02*C
L
*f
S
(in mA) with V
CC
= 3.3V, T
A
= 25
°
C, f
S
= WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at f
S
/2,
C
L
= capacitive load (in pF).
6. All Inputs = V
CC
- 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
(2)
C
OUT
(1,2)
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
10
10
Unit
pF
pF
NOTES:
1. With output deselected (OE
≥
V
IH
).
2. Characterized values, not currently tested.
3
IDT72V10081/11081/12081/13081/14081 3.3V MULTIMEDIA FIFO
256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8
INDUSTRIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(1)
(Industrial: V
CC
= 3.3 ±0.3V, TA = -40°C to + 85°C)
Industrial
IDT72V10081L15
IDT72V11081L15
IDT72V12081L15
IDT72V13081L15
IDT72V14081L15
Symbol
f
S
t
A
t
CLK
t
CLKH
t
CLKL
t
DS
t
DH
t
ENS
t
ENH
t
RS
t
RSS
t
RSR
t
RSF
t
OLZ
t
OE
t
OHZ
t
WFF
t
REF
t
SKEW1
Parameter
Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Clock High Time
Clock Low Time
Data Setup Time
Data Hold Time
Enable Setup Time
Enable Hold Time
Reset Pulse Width
(1)
Reset Setup Time
Reset Recovery Time
Reset to Flag and Output Time
Output Enable to Output in Low-Z
Output Enable to Output Valid
Output Enable to Output in High-Z
(2)
Write Clock to Full Flag
Read Clock to Empty Flag
Skew time between Read Clock & Write
Clock for Empty Flag &Full Flag
(2)
Min.
—
2
15
6
6
4
1
4
1
15
10
10
—
0
3
3
—
—
6
Max.
66.7
10
—
—
—
—
—
—
—
—
—
—
15
—
8
8
10
10
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Pulse widths less than minimum values are not allowed.
2. Values guaranteed by design, not currently tested.
3.3V
330Ω
D.U.T.
AC TEST CONDITIONS
In Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1
510Ω
30pF*
6161 drw03
or equivalent circuit
Figure 1. Output Load
*Includes jig and scope capacitances.
4
IDT72V10081/11081/12081/13081/14081 3.3V MULTIMEDIA FIFO
256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8
INDUSTRIAL TEMPERATURE RANGE
SIGNAL DESCRIPTIONS
INPUTS
DATA IN (D0 - D7)
Data inputs for 8-bit wide data.
CONTROLS
RESET (RS)
Reset is accomplished whenever the Reset (RS) input is taken to a LOW state.
During reset, both internal read and write pointers are set to the first location.
A reset is required after power-up before a write operation can take place. The
Full Flag (FF) will be reset to HIGH after t
RSF
. The Empty Flag (EF) will be
reset to LOW after t
RSF
. During reset, the output register is initialized to all zeros.
WRITE CLOCK (WCLK)
A write cycle is initiated on the LOW-to-HIGH transition of the Write Clock
(WCLK). Data setup and hold times must be met in respect to the LOW-to-HIGH
transition of the Write Clock (WCLK). The Full Flag (FF) is synchronized with
respect to the LOW-to-HIGH transition of the Write Clock (WCLK).
The Write and Read clocks can be asynchronous or coincident.
WRITE ENABLE (WEN)
When Write Enable (WEN) is low, data can be loaded into the input register
and FIFO array on the LOW-to-HIGH transition of every Write Clock (WCLK).
Data is stored in the FIFO array sequentially and independently of any on-going
read operation.
To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting further
write operations. Upon the completion of a valid read cycle, the Full Flag (FF)
will go HIGH after t
WFF
, allowing a valid write to begin. Write Enable (WEN)
is ignored when the FIFO is full.
READ CLOCK (RCLK)
Data can be read on the outputs on the LOW-to-HIGH transition of the Read
Clock (RCLK). The Empty Flag (EF)is synchronized with respect to the LOW-
to-HIGH transition of the Read Clock (RCLK).
The Write and Read clocks can be asynchronous or coincident.
READ ENABLES (REN)
When both Read Enable (REN) is LOW, data is read from the FIFO array
to the output register on the LOW-to-HIGH transition of the Read Clock (RCLK).
When Read Enable (REN) is HIGH, the output register holds the previous
data and no new data is allowed to be loaded into the register.
When all the data has been read from the FIFO, the Empty Flag (EF) will go
LOW, inhibiting further read operations. Once a valid write operation has been
accomplished, the Empty Flag (EF) will go HIGH after t
REF
and a valid read
can begin. The Read Enable (REN) is ignored when the FIFO is empty.
OUTPUT ENABLE (OE)
When Output Enable (OE) is enabled (LOW), the parallel output buffers
receive data from the output register. When Output Enable (OE) is disabled
(HIGH), the Q output data bus is in a high-impedance state.
OUTPUTS
FULL FLAG (FF)
The Full Flag (FF) will go LOW, inhibiting further write operation, when the
device is full. If no reads are performed after Reset (RS), the Full Flag (FF)
will go LOW after 256 writes for the IDT72V10081, 512 writes for the
IDT72V11081, 1,024 writes for the IDT72V12081, 2,048 writes for the
IDT72V13081 and 4,096 writes for the IDT72V14081.
The Full Flag (FF) is synchronized with respect to the LOW-to-HIGH
transition of the Write Clock (WCLK).
EMPTY FLAG (EF)
The Empty Flag (EF) will go LOW, inhibiting further read operations, when
the read pointer is equal to the write pointer, indicating the device is empty.
The Empty Flag (EF) is synchronized with respect to the LOW-to-HIGH
transition of the Read Clock (RCLK).
DATA OUTPUTS (Q
0
- Q7)
Data outputs for a 8-bit wide data.
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