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IDT74ALVCH16500PA8

Registered Bus Transceiver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, 0.50 MM PITCH, TSSOP-56

器件类别:逻辑    逻辑   

厂商名称:IDT (Integrated Device Technology)

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器件参数
参数名称
属性值
厂商名称
IDT (Integrated Device Technology)
零件包装代码
TSSOP
包装说明
TSSOP,
针数
56
Reach Compliance Code
unknown
其他特性
WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
系列
ALVC/VCX/A
JESD-30 代码
R-PDSO-G56
JESD-609代码
e0
长度
14 mm
逻辑集成电路类型
REGISTERED BUS TRANSCEIVER
位数
18
功能数量
1
端口数量
2
端子数量
56
最高工作温度
85 °C
最低工作温度
-40 °C
输出特性
3-STATE
输出极性
TRUE
封装主体材料
PLASTIC/EPOXY
封装代码
TSSOP
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟(tpd)
6.6 ns
认证状态
Not Qualified
座面最大高度
1.2 mm
最大供电电压 (Vsup)
3.6 V
最小供电电压 (Vsup)
2.7 V
标称供电电压 (Vsup)
3.3 V
表面贴装
YES
技术
CMOS
温度等级
INDUSTRIAL
端子面层
TIN LEAD
端子形式
GULL WING
端子节距
0.5 mm
端子位置
DUAL
宽度
6.1 mm
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IDT74ALVCH16500
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 18-BIT UNIVERSAL
BUS TRANSCEIVER WITH
3-STATE OUTPUTS
AND BUS-HOLD
• 0.5 MICRON CMOS Technology
• Typical t
SK(o)
(Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• V
CC
= 3.3V ± 0.3V, Normal Range
• V
CC
= 2.7V to 3.6V, Extended Range
• V
CC
= 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
µ
• Rail-to-Rail output swing for increased noise margin
• Available in SSOP, TSSOP, and TVSOP packages
IDT74ALVCH16500
FEATURES:
DESCRIPTION:
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for heavy loads
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
This 18-bit universal bus transceiver is built using advanced dual metal
CMOS technology. Data flow in each direction is controlled by output-enable
(OEAB and
OEBA),
latch enable (LEAB and LEBA) and clock (CLKAB and
CLKBA)
inputs. For A-to-B data flow, the device operates in transparent mode
when LEAB is high. When LEAB is LOW, the A data is latched if
CLKAB
is held
at a high or low logic level. If LEAB is LOW, the A bus data is stored in the latch/
flip-flop on the high-to-low transition of
CLKAB.
OEAB performs the output enable
function on the B port. Data flow from B port to A port is similiar but requires using
OEBA,
LEBA and
CLKBA.
Flow-through organization of signal pins simplifies
layout. All inputs are designed with hysteresis for improved noise margin.
The ALVCH16500 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining speed
performance.
The ALVCH16500 has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
O EAB
CLKAB
1
55
LEAB
LEBA
C LKBA
OEBA
2
28
30
27
A
1
3
1D
C1
CLK
54
B
1
1D
C1
CLK
TO 17 OTH ER CHANN ELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 1999 Integrated Device Technology, Inc.
APRIL 1999
DSC-4539/2
IDT74ALVCH16500
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
OEAB
LEAB
A
1
GND
A
2
A
3
V
CC
A
4
A
5
A
6
GND
A
7
A
8
A
9
A
10
A
11
A
12
GND
A
13
A
14
A
15
V
CC
A
16
A
17
GND
A
18
OEBA
LEBA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Max
V
TERM
(2)
Terminal Voltage with Respect to GND
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
CLKAB
B
1
GND
B
2
B
3
V
CC
B
4
B
5
B
6
GND
B
7
B
8
B
9
B
10
B
11
B
12
GND
B
13
B
14
B
15
V
CC
B
16
B
17
GND
B
18
CLKBA
GND
Unit
V
V
°C
mA
mA
mA
mA
–0.5 to +4.6
–0.5 to V
CC
+0.5
–65 to +150
–50 to +50
±50
–50
±100
V
TERM
(3)
Terminal Voltage with Respect to GND
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
I
> V
CC
Continuous Clamp Current, V
O
< 0
Continuous Current through each
V
CC
or GND
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
OUT
C
I/O
Parameter
(1)
Input Capacitance
Output Capacitance
I/O Port Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
5
7
7
Max.
7
9
9
Unit
pF
pF
pF
NOTE:
1. As applicable to the device type.
PIN DESCRIPTION
Pin Names
Description
A-to-B Output Enable Input
B-to-A Output Enable Input (Active LOW)
A-to-B Latch Enable Input
B-to-A Latch Enable Input
A-to-B Clock Input
B-to-A Clock Input
A-to-B Data Inputs or B-to-A 3-State Outputs
(1)
B-to-A Data Inputs or A-to-B 3-State Outputs
(1)
OEAB
OEBA
LEAB
LEBA
CLKAB
CLKBA
Ax
Bx
SSOP/ TSSOP/ TVSOP
TOP VIEW
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
2
IDT74ALVCH16500
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
FUNCTION TABLE
(1,2)
Inputs
OEAB
L
H
H
H
H
H
LEAB
X
H
H
L
L
L
CLKAB
X
X
X
L or H
Ax
X
L
H
L
H
X
Output
Bx
Z
L
H
L
H
B
(3)
NOTES:
1. A-to-B data flow is shown. B-to-A data flow is similar, but uses
OEBA,
LEBA, and
CLKBA.
2. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
= HIGH-to-LOW Transition
3. Output level before the indicated steady-state input conditions were established.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= –40°C to +85°C
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input HIGH Current
Input LOW Current
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= 2.3V, I
IN
= –18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
One input at V
CC
- 0.6V, other inputs at V
CC
or GND
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
I
= V
CC
V
I
= GND
V
O
= V
CC
V
O
= GND
Test Conditions
Min.
1.7
2
Typ.
(1)
–0.7
100
0.1
Max.
0.7
0.8
±5
±5
±10
±10
–1.2
40
V
mV
µA
µA
µA
µA
V
Unit
V
Quiescent Power Supply Current
Variation
750
µA
NOTE:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
3
IDT74ALVCH16500
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
BUS-HOLD CHARACTERISTICS
Symbol
I
BHH
I
BHL
I
BHH
I
BHL
I
BHHO
I
BHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
Parameter
(1)
Bus-Hold Input Sustain Current
Bus-Hold Input Sustain Current
Bus-Hold Input Overdrive Current
V
CC
= 3V
V
CC
= 2.3V
V
CC
= 3.6V
Test Conditions
V
I
= 2V
V
I
= 0.8V
V
I
= 1.7V
V
I
= 0.7V
V
I
= 0 to 3.6V
Min.
– 75
75
– 45
45
Typ.
(2)
Max.
±500
Unit
µA
µA
µA
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
= 2.3V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
V
CC
= 3V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
I
OH
= – 24mA
I
OL
= 0.1mA
I
OL
= 6mA
I
OL
= 12mA
I
OL
= 12mA
I
OL
= 24mA
Test Conditions
(1)
V
CC
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 6mA
I
OH
= – 12mA
Min.
V
CC
– 0.2
2
1.7
2.2
2.4
2
Max.
0.2
0.4
0.7
0.4
0.55
V
Unit
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate V
CC
range.
T
A
= – 40°C to + 85°C.
OPERATING CHARACTERISTICS, T
A
= 25°C
V
CC
= 2.5V ± 0.2V
Symbol
C
PD
C
PD
Parameter
Power Dissipation Capacitance Outputs enabled
Power Dissipation Capacitance Outputs disabled
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
40
6
V
CC
= 3.3V ± 0.3V
Typical
51
6
Unit
pF
4
IDT74ALVCH16500
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS
(1)
V
CC
= 2.5V ± 0.2V
Symbol
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PHZ
t
PLZ
t
SU
t
SU
t
H
t
H
t
W
t
W
t
SK
(o)
Propagation Delay
Ax to Bx or Bx to Ax
Propagation Delay
LEBA to Ax or LEAB to Bx
Propagation Delay
CLKBA
to Ax or
CLKAB
to Bx
Output Enable Time
OEBA
to Ax
Output Enable Time
OEAB toBx
Output Disable Time
OEBA
to Ax
Output Disable Time
OEAB toBx
Set-up Time, HIGH or LOW, Ax to
CLKAB
or Bx to
CLKBA
Set-up Time, HIGH or LOW,
Ax to LEAB or Bx to LEBA
Hold Time, HIGH or LOW,
Ax to LEAB or Bx to LEBA
Pulse Width, LE HIGH
Pulse Width,
CLK
HIGH or LOW
Output Skew
(2)
CLK
LOW
CLK
HIGH
CLK
LOW
CLK
HIGH
1.7
1.9
1.1
1.7
1.6
2
3.3
3.3
1.4
1.6
1
1.6
1.5
1.8
3.3
3.3
1.3
1.4
1
1.3
1.2
1.5
3.3
3.3
500
ns
ns
ps
ns
ns
ns
ns
1
6.1
5.7
1.5
5
ns
1
5.4
4.6
1
4.3
ns
1
5.7
5.4
1
4.6
ns
1
6.2
6.2
1
5.2
ns
1
6.6
6.6
1.1
5.5
ns
1
5.9
5.5
1
4.7
ns
Parameter
Min.
150
1
Max.
5.1
V
CC
= 2.7V
Min.
150
Max.
4.7
V
CC
= 3.3V ± 0.3V
Min.
150
1
Max.
3.9
Unit
MHz
ns
Hold Time, HIGH or LOW, Ax to
CLKAB
or Bx to
CLKBA
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. T
A
= – 40°C to + 85°C.
2 Skew between any two outputs of the same package and switching in the same direction.
5
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参数对比
与IDT74ALVCH16500PA8相近的元器件有:IDT74ALVCH16500PF8、IDT74ALVCH16500PV8。描述及对比如下:
型号 IDT74ALVCH16500PA8 IDT74ALVCH16500PF8 IDT74ALVCH16500PV8
描述 Registered Bus Transceiver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, 0.50 MM PITCH, TSSOP-56 Registered Bus Transceiver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, 0.40 MM PITCH, TVSOP-56 Registered Bus Transceiver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, 0.635 MM PITCH, SSOP-56
厂商名称 IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology)
零件包装代码 TSSOP SSOP SSOP
包装说明 TSSOP, TSSOP, SSOP,
针数 56 56 56
Reach Compliance Code unknown unknown unknown
其他特性 WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
系列 ALVC/VCX/A ALVC/VCX/A ALVC/VCX/A
JESD-30 代码 R-PDSO-G56 R-PDSO-G56 R-PDSO-G56
JESD-609代码 e0 e0 e0
长度 14 mm 11.3 mm 18.415 mm
逻辑集成电路类型 REGISTERED BUS TRANSCEIVER REGISTERED BUS TRANSCEIVER REGISTERED BUS TRANSCEIVER
位数 18 18 18
功能数量 1 1 1
端口数量 2 2 2
端子数量 56 56 56
最高工作温度 85 °C 85 °C 85 °C
最低工作温度 -40 °C -40 °C -40 °C
输出特性 3-STATE 3-STATE 3-STATE
输出极性 TRUE TRUE TRUE
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 TSSOP TSSOP SSOP
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH
传播延迟(tpd) 6.6 ns 6.6 ns 6.6 ns
认证状态 Not Qualified Not Qualified Not Qualified
座面最大高度 1.2 mm 1.2 mm 2.794 mm
最大供电电压 (Vsup) 3.6 V 3.6 V 3.6 V
最小供电电压 (Vsup) 2.7 V 2.7 V 2.7 V
标称供电电压 (Vsup) 3.3 V 3.3 V 3.3 V
表面贴装 YES YES YES
技术 CMOS CMOS CMOS
温度等级 INDUSTRIAL INDUSTRIAL INDUSTRIAL
端子面层 TIN LEAD TIN LEAD TIN LEAD
端子形式 GULL WING GULL WING GULL WING
端子节距 0.5 mm 0.4 mm 0.635 mm
端子位置 DUAL DUAL DUAL
宽度 6.1 mm 4.4 mm 7.5 mm
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L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ
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