Quad Port PHY (Physical Layer)
for 25.6 and 51.2
ATM Networks
Features List
Performs the PHY-Transmission Convergence (TC) and
Physical Media Dependent (PMD) Sublayer functions for
four 25.6 Mbps ATM channels
Compliant to ATM Forum (af-phy-040.000) and ITU-T I.432.5
specifications for 25.6 Mbps physical interface
Also operates at 51.2 Mbps data rate
UTOPIA Level 1, UTOPIA Level 2, or DPI-4 Interface
3-Cell Transmit & Receive FIFOs
LED Interface for status signalling
Supports UTP Category 3 and 5 physical media
Interfaces to standard magnetics
Low-Power CMOS
3.3V supply with 5V tolerant inputs
144-pin PQFP Package (28 x 28 mm)
Commercial and Industrial Temperature Ranges
IDT77V1254L25
Description
The IDT77V1254L25 is a member of IDT's family of products
supporting Asynchronous Transfer Mode (ATM) data communications
and networking. The IDT77V1254L25 implements the physical layer for
25.6 Mbps ATM, connecting four serial copper links (UTP Category 3
and 5) to one ATM layer device such as a SAR or a switch ASIC. The
IDT77V1254L25 also operates at 51.2 Mbps, and is well suited to back-
plane driving applications.
The 77V1254L25-to-ATM layer interface is selectable as one of three
options: 16-bit UTOPIA Level 2, 8-bit UTOPIA Level 1 Multi-PHY, or
quadruple 4-bit DPI (Data Path Interface).
The IDT77V1254L25 is fabricated using IDT's state-of-the-art CMOS
technology, providing the highest levels of integration, performance and
reliability, with the low-power consumption characteristics of CMOS.
Block Diagram
TXREF
T X C LK
T X D A T A [15:0]
T X P A R IT Y
TX S O C
TXEN
T X C LA V
T X A D D R [4:0]
M O D E [1:0]
P H Y -A T M
Interface
(U T O P IA or D P I)
D ri
ver
T X /R X A T M
C el IF O
lF
S cram bl
er/
D escram bl
er
5B /4B
E ncodi
ng/
D ecodi
ng
P /S and S /P
N R ZI
+
Tx 1
-
+
Rx1
-
D ri
ver
T X /R X A T M
C el IF O
lF
S cram bl
er/
D escram bl
er
5B /4B
E ncodi
ng/
D ecodi
ng
P /S and S /P
N R ZI
+
TX 0
-
+
RX 0
-
C l R ecovery
ock
R X A D D R [4:0]
R X C LK
R X D A T A [15:0]
R X P A R IT Y
R XSO C
RXEN
R X C LA V
C l R ecovery
ock
INT
RST
D ri
ver
T X /R X A T M
C el IF O
lF
Mi
croprocessor
Interface
S cram bl
er/
D escram bl
er
5B /4B
E ncodi
ng/
D ecodi
ng
P /S and S /P
N R ZI
C l R ecovery
ock
+
- TX 2
+
-RX 2
RD
WR
CS
A D [7:0]
A LE
T X /R X A T M
C el IF O
lF
O SC
S cram bl
er/
D escram bl
er
5B /4B
E ncodi
ng/
D ecodi
ng
P /S and S /P
N R ZI
D ri
ver
+
- TX 3
+
-RX 3
C l R ecovery
ock
4
4
RXREF
R X LE D [3:0]
T X LE D [3:0]
35 0 5 drw 0 1
.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 47
2001 Integrated Device Technology, Inc.
September 21, 2001
DSC 6003
IDT77V1254L25
Applications
Up to 204.8Mbps backplane transmission
Rack-to-rack short links
ATM Switches
Operation AT 51.2 Mbps
In addition to operation at the standard rate of 25.6 Mbps, the
77V1254L25 is also specified to operate at 51.2 Mbps. Except for the
doubled bit rate, all other aspects of operation are identical to the 25.6
Mbps mode.
The rate is determined by the frequency of the clock applied to the
OSC input pin. OSC is 32 MHz for the 25.6 Mbps line rate, and 64 MHz
for the 51.2 Mbps line rate. All ports operate at the same frequency.
See Figure 36 for recommended line magnetics. Magnetics for 51.2
Mbps operation have a higher bandwidth than magnetics optimized for
25.6 Mbps.
77V1254L25 Overview
The 77V1254L25 is a four port implementation of the physical layer
standard for 25.6Mbps ATM network communications as defined by
ATM Forum document af-phy-040.000 and ITU-T I.432.5. The physical
layer is divided into a Physical Media Dependent sub layer (PMD) and
Transmission Convergence (TC) sub layer. The PMD sub layer includes
the functions for the transmitter, receiver and clock recovery for opera-
tion across 100 meters of category 3 and 5 unshielded twisted pair
(UTP) cable. This is referred to as the Line Side Interface. The TC sub
layer defines the line coding, scrambling, data framing and synchroniza-
tion.
On the other side, the 77V1254L25 interfaces to an ATM layer device
(such as a switch core or SAR). This cell level interface is configurable
as either 8-bit Utopia Level 1 Multi-PHY, 16-bit Utopia Level 2, or as four
4-bit DPI interfaces, as determined by two MODE pins. This is referred
to as the PHY-ATM Interface. The pinout and front page block diagram
are based on the Utopia 2 configuration. Table 2 shows the corre-
sponding pin functions for the other two modes, and Figure 2 and Figure
3 show functional block diagrams.
The 77V1254L25 is based on the 77105, and maintains significant
register compatibility with it. The 77V1254L25, however, has additional
register features, and also duplicates most of its registers to provide
significant independence between the four ports.
Access to these status and control registers is through the utility bus.
This is an 8-bit muxed address and data bus, controlled by a conven-
tional asynchronous read/write handshake.
Additional pins permit insertion and extraction of an 8kHz timing
marker, and provide LED indication of receive and transmit status.
Auto-Synchronization and Good Signal
Indication
The 77V1254L25 features a new receiver synchronization algorithm
that allow it to achieve 4b/5b symbol framing on any valid data stream.
This is an improvement on earlier products which could frame only on
the escape symbol, which occurs only in start-of-cell or 8kHz (X8) timing
marker symbol pairs.
ATM25 transceivers always transmit valid 4b/5b symbols, allowing
the 77V1254L25 receive section to achieve symbol framing and properly
indicate receive signal status, even in the absence of ATM cells or 8kHz
(X8) timing markers in the receive data stream. A state maching moni-
tors the received symbols and asserts the “Good Signal” status bit when
a valid signal is being received. “Good Signal” is deasserted and the
receive FIFO is disabled when the signal is lost. This is sometimes
referred to as Loss of Signal (LOS).
Functional Description
Transmission Convergence (TC) Sub Layer
Introduction
The TC sub layer defines the line coding, scrambling, data framing
and synchronization. Under control of a switch interface or Segmenta-
tion and Reassembly (SAR) unit, the 25.6Mbps ATM PHY accepts a 53-
byte ATM cell, scrambles the data, appends a command byte to the
beginning of the cell, and encodes the entire 53 bytes before transmis-
sion. These data transformations ensure that the signal is evenly distrib-
uted across the frequency spectrum. In addition, the serialized bit
stream is NRZI coded. An 8kHz timing sync pulse may be used for
isochronous communications.
Data Structure and Framing
Each 53-byte ATM cell is preceded with a command byte. This byte
is distinguished by an escape symbol followed by one of 17 encoded
symbols. Together, this byte forms one of seventeen possible command
bytes. Three command bytes are defined:
1.
X_X
(read: 'escape' symbol followed by another 'escape'): Start-
of-cell with scrambler/descrambler reset.
2.
X_4
('escape' followed by '4'): Start-of-cell without scrambler/
descrambler reset.
3.
X_8
('escape' followed by '8'): 8kHz timing marker. This
command byte is generated when the 8kHz sync pulse is
detected, and has priority over all line activity (data or command
bytes). It is transmitted immediately when the sync pulse is
detected. When this occurs during a cell transmission, the data
transfer is temporarily interrupted on an octet boundary, and the
X_8 command byte is inserted. This condition is the only allowed
interrupt in an otherwise contiguous transfer.
Below is an illustration of the cell structure and command byte
usage:
{X_X} {53-byte ATM cell} {X_4} {53-byte ATM {X_8} cell} ...
In the above example, the first ATM cell is preceded by the X_X
start-of-cell command byte which resets both the transmitter-scrambler
and receiver-descrambler pseudo-random nibble generators (PRNG) to
their initial states. The following cell illustrates the insertion of a start-of-
cell command without scrambler/descrambler reset. During this cell's
transmission, an 8kHz timing sync pulse triggers insertion of the X_8
8kHz timing marker command byte.
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September 21, 2001
IDT77V1254L25
Transmission Description
Refer to Figure 4. Cell transmission begins with the PHY-ATM Inter-
face. An ATM layer device transfers a cell into the 77V1254L25 across
the Utopia or DPI transmit bus. This cell enters a 3-cell deep transmit
FIFO. Once a complete cell is in the FIFO, transmission begins by
passing the cell, four bits (MSB first) at a time to the 'Scrambler'.
The 'Scrambler' takes each nibble of data and exclusive-ORs them
against the 4 high order bits (X(t), X(t-1), X(t-2), X(t-3)) of a 10 bit
pseudo-random nibble generator (PRNG). Its function is to provide the
appropriate frequency distribution for the signal across the line.
The PRNG is clocked every time a nibble is processed, regardless of
whether the processed nibble is part of a data or command byte. Note
however that only data nibbles are scrambled. The entire command byte
(X _C) is NOT scrambled before it's encoded (see diagram for illustra-
tion). The PRNG is based upon the following polynomial:
X
10
+ X
7
+ 1
With this polynomial, the four output data bits (D3, D2, D1, D0) will be
generated from the following equations:
D3 = d3 xor X(t-3)
D2 = d2 xor X(t-2)
D1 = d1 xor X(t-1)
D0 = d0 xor X(t)
The following nibble is scrambled with X(t+4), X(t+3), X(t+2), and
X(t+1).
A scrambler lock between the transmitter and receiver occurs each
time an X_X command is sent. An X_X command is initiated only at the
beginning of a cell transfer after the PRNG has cycled through all of its
states (2
10
- 1 = 1023 states). The first valid ATM data cell transmitted
after power on will also be accompanied with an X_X command byte.
Each time an X_X command byte is sent, the first nibble after the last
escape (X) nibble is XOR'd with 1111b (PRNG = 3FFx).
Because a timing marker command (X_8) may occur at any time, the
possibility of a reset PRNG start-of-cell command and a timing marker
command occurring consecutively does exist (e.g. X_X_X_8). In this
case, the detection of the last two consecutive escape (X) nibbles will
cause the PRNG to reset to its initial 3FFx state. Therefore, the PRNG is
clocked only after the first nibble of the second consecutive escape pair.
Once the data nibbles have been scrambled using the PRNG, the
nibbles are further encoded using a 4b/5b process. The 4b/5b scheme
ensures that an appropriate number of signal transitions occur on the
line. A total of seventeen 5-bit symbols are used to represent the sixteen
4-bit data nibbles and the one escape (X) nibble. The table below lists
the 4-bit data with their corresponding 5-bit symbols:
'DWD
6\PERO
'DWD
6\PERO
'DWD
6\PERO
'DWD
6\PERO
GUZ D
This encode/decode implementation has several very desirable prop-
erties. Among them is the fact that the output data bits can be repre-
sented by a set of relatively simple symbols;
Run length is limited to <= 5;
Disparity never exceeds +/- 1.
On the receiver, the decoder determines from the received symbols
whether a timing marker command (X_8) or a start-of-cell command was
sent (X_X or X_4). If a start-of-cell command is detected, the next 53
bytes received are decoded and forwarded to the descrambler. (See TC
Receive Block Diagram, Figure 5).
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September 21, 2001
IDT77V1254L25
9''
*1'
7;
7;
9''
00
02'(
02'(
RXREF
TXREF
*1'
7;/('
7;/('
7;/('
7;/('
9''
7;'$7$
7;'$7$
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7;'$7$
7;3$5,7<
TXEN
7;62&
7;$''5
7;
7;
*1'
$*1'
$9''
5;
5;
$9''
$*1'
$*1'
$9''
5;
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$9''
$*1'
$*1'
$9''
$*1'
26&
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77V1254L25
9
34)3
9''
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7;
9''
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6(
$'
$'
$'
$'
*1'
$'
$'
$'
$'
9''
$/(
CS
RD
WR
RST
*1'
INT
9''
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.
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7;&/$9
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5;&/.
RXEN
5;$''5
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5;&/$9
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GUZ
Figure 1 Pin Assignments
4 of 47
September 21, 2001
IDT77V1254L25
Signal Descriptions
Line Side Signals
Signal Name
RX0+,-
RX1+,-
RX2+,-
RX3+,-
TX0+,-
TX1+,-
TX2+,-
TX3+,-
Pin Number
139, 138
133, 132
121, 120
115, 114
4, 3
144, 143
110, 109
106, 105
I/O
In
In
In
In
Out
Out
Out
Out
Signal Description
Port 0 positive and negative receive differential input pair.
Port 1 positive and negative receive differential input pair.
Port 2 positive and negative receive differential input pair.
Port 3 positive and negative receive differential input pair.
Port 0 positive and negative transmit differential output pair.
Port 1 positive and negative transmit differential output pair.
Port 2 positive and negative transmit differential output pair.
Port 3 positive and negative transmit differential output pair.
Utility Bus Signals
Signal Name
AD[7:0]
ALE
CS
RD
WR
Pin Number
I/O
Signal Description
101, 100, 99, 98, 96, 95, 94, In/Out Utility bus address/data bus. The address input is sampled on the falling edge of ALE. Data is output on this
93
bus when a read is performed. Input data is sampled at the completion of a write operation.
91
90
89
88
In
In
In
Utility bus address latch enable. Asynchronous input. An address on the AD bus is sampled on the falling
edge of ALE. ALE must be low when the AD bus is being used for data.
Utility bus asynchronous chip select. CS must be asserted to read or write an internal register. It may remain
asserted at all times if desired
Utility bus read enable. Active low asynchronous input. After latching an address, a read is performed by
deasserting WR and asserting RD and CS.
Utility bus write enable. Active low asynchronous input. After latching an address, a write is performed by
deasserting RD, placing data on the AD bus, and asserting WR and CS. Data is sampled when WR or CS is
deasserted.
Miscellaneous Signals
Signal Name
DA
INT
Pin Number
103
85
I/O
In
Out
Signal Description
Reserved signal. This input must be connected to logic low.
Interrupt. INT is an open-drain output, driven low to indicate an interrupt. Once low, INT remains low until the
interrupt status in the appropriate interrupt Status Register is read. Interrupt sources are programmable via
the interrupt Mask Registers.
Reserved signal. This input must be connected to logic low.
Mode Selects. They determine the configuration of the PHY/ATM interface. 00 = UTOPIA Level 2. 01 = UTO-
PIA Level 1. 10 = DPI. 11 is reserved.
TTL line rate clock source, driven by a 100 ppm oscillator. 32 MHz for 25.6 Mbps; 64 MHz for 51.2 Mbps.
Reset. Active low asynchronous input resets all control logic, counters and FIFOs. A reset must be per-
formed after power up prior to normal operation of the part.
Receive LED drivers. Driven low for 223 cycles of OSC, beginning with RXSOC when that port receives a
good (non-null and non-errored) cell. Drives 8 mA both high and low. One per port.
Receive Reference. Active low, synchronous to OSC. RXREF pulses low for a programmable number of
clock cycles when an x_8 command byte is received. Register 0x40 is programmed to indicate which port is
referenced.
Reserved signal. This input must be connected to logic low.
Table 1 Signal Descriptions (Part 1 of 3)
MM
MODE[1:0]
OSC
RST
RXLED[3:0]
RXREF
6
7, 8
126
87
82, 81, 80, 79
9
In
In
In
In
Out
Out
SE
102
In
5 of 47
September 21, 2001
