512K x 8
CMOS STATIC RAM MODULE
Integrated Device Technology, Inc.
IDT7MB4048
FEATURES:
• High-density 4-megabit (512K x 8) Static RAM module
• Fast access time: 25ns (max.)
Surface mounted plastic packages on a 32-pin, 600 mil
FR-4 DIP substrate
• Single 5V (±10%) power supply
• Inputs/outputs directly TTL-compatible
DESCRIPTION:
The IDT7MB4048 is a 4-megabit (512K x 8) Static RAM
module constructed on a multilayer epoxy laminate (FR-4)
substrate using four 1 megabit SRAMs and a decoder. The
IDT7MB4048 is available with access times as fast as 25ns.
The IDT7MB4048 is packaged in a 32-pin FR-4 DIP resulting
in the JEDEC footprint in a package 1.6 inches long and 0.6
inches wide.
All inputs and outputs of the IDT7MB4048 are TTL-com-
patible and operate from a single 5V supply. Fully asynchro-
nous circuitry requires no clocks or refresh for operation and
provides equal access and cycle times for ease of use.
PIN CONFIGURATION
A
18
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
FUNCTIONAL BLOCK DIAGRAM
Vcc
A
15
A
17
A
13
A
8
A
9
A
11
A
10
ADDRESS
19
512K x 8
RAM
WE
OE
CS
WE
OE
CS
8
I/O
2675 drw 02
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
2675 drw 01
DIP
TOP VIEW
PIN NAMES
I/O
0-7
A
0-18
Data Inputs/Outputs
Addresses
Chip Select
Write Enable
Output Enable
Power
Ground
2675 tbl 01
CS
WE
OE
V
CC
GND
The IDT logo is a registered trademark of Integrated Device Technology Inc.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
DECEMBER 1995
DSC-2675/6
7.11
1
IDT7MB4048
512K x 8 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TRUTH TABLE
Mode
Standby
Read
Read
Write
ABSOLUTE MAXIMUM RATINGS
(1)
CS
H
L
L
L
OE
X
L
H
X
WE
X
H
H
L
Output
High-Z
D
OUT
High-Z
D
IN
Power
Standby
Active
Active
Active
2675 tbl 02
Symbol
V
TERM
Rating
Terminal Voltage
with Respect
to GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
DC Output Current
Commercial
–0.5 to +7.0
Unit
V
T
A
T
BIAS
T
STG
0 to +70
–10 to +85
–55 to +125
50
°C
°C
°C
mA
CAPACITANCE
(1)
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
IN(C)
C
OUT
Parameter
Input Capacitance
Input Capacitance (
CS
)
Output Capacitance
Conditions
V
IN
= 0V
V
IN
= 0V
V
OUT
= 0V
Typ. Unit
35
8
35
pF
pF
pF
2675 tbl 03
I
OUT
NOTE:
1. This parameter is guaranteed by design, but not tested.
NOTE:
2675 tbl 05
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS RECOMMENDED OPERATING
Symbol
Parameter
Min.
Typ.
Max. Unit
TEMPERATURE AND SUPPLY VOLTAGE
V
CC
GND
V
IH
V
IL
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
4.5
0
2.2
–0.5
(1)
5
0
—
—
5.5
0
6
0.8
V
V
V
V
2675 tbl 04
Grade
Commercial
Ambient
Temperature
0°C to +70°C
GND
0V
V
CC
5V
±
10%
2675 tbl 06
NOTE:
1. V
IL
= –2.0V for pulse width less than 10ns.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 5V
±
10%, T
A
= 0°C to +70°C)
7MB4048SxxP
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
I
CC
I
SB
I
SB1
Parameter
Input Leakage
Output Leakage
Output Low Voltage
Output High Voltage
Dynamic Operating Current
Standby Supply Current
(TTL Levels)
Full Standby Supply Current
(CMOS Levels)
Test Conditions
V
CC
= Max., V
IN
= GND to V
CC
V
CC
= Max.,
CS
= V
IH
,
V
OUT
= GND to V
CC
V
CC
= Min., I
OL
= 8mA
V
CC
= Min., I
OH
= –1mA
V
CC
= Max.,
CS
≤
V
IL
; f = f
MAX
,
Outputs Open
Min.
—
—
—
2.4
—
Max. Unit
8
8
0.4
—
480
250
170
µA
µA
V
V
mA
mA
mA
2675 tbl 07
CS
≥
V
IH
, V
CC
= Max., f = f
MAX
,
Outputs Open
—
CS
≥
V
CC
- 0.2V, V
IN
≥
V
CC
- 0.2V
or
≤
0.2
—
7.11
2
IDT7MB4048
512K x 8 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 & 2
2675 tbl 09
+5 V
+5 V
480
Ω
DATA
OUT
255Ω
30 pF*
480
Ω
DATA
OUT
255Ω
5 pF*
2675 drw 04
2675 drw 05
Figure 1. Output Load
Figure 2. Output Load
(for t
OLZ
, t
CHZ
, t
OHZ
, t
WHZ
, t
OW
and t
CLZ
)
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5V
±
10%, T
A
= 0°C to +70°C)
7MB4048
–25
–30
–35
Symbol
Read Cycle
t
RC
t
AA
t
ACS
t
OE
t
OHZ(1)
t
OLZ(1)
t
CLZ
t
OH
t
PU(1)
t
PD(1)
t
WC
t
WP
t
AS(2)
t
AW
t
CW
t
DW
t
DH(2)
t
WR(2)
t
OW(1)
(1)
(1)
Parameter
Min. Max.
25
—
—
—
—
0
5
—
3
0
—
25
17
3
20
20
15
0
0
—
2
—
25
25
12
12
—
—
14
—
—
25
—
—
—
—
—
—
—
—
15
—
Min. Max.
30
—
—
—
—
0
5
—
3
0
—
30
20
0
25
25
17
0
0
—
5
—
30
30
15
12
—
—
16
—
—
30
—
—
—
—
—
—
—
—
15
—
Min. Max. Unit
35
—
—
—
—
0
5
—
3
0
—
35
25
0
30
30
20
0
0
—
5
—
35
35
15
15
—
—
20
—
—
35
—
—
—
—
—
—
—
—
15
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Output Disable to Output in High-Z
Output Enable to Output in Low-Z
Chip Select to Output in Low-Z
Chip Deselect to Output in High-Z
Output Hold from Address Change
Chip Select to Power-Up Time
Chip Deselect to Power-Down Time
Write Cycle Time
Write Pulse Width
Address Set-up Time
Address Valid to End-of-Write
Chip Select to End-of-Write
Data to Write Time Overlap
Data Hold Time
Write Recovery Time
Output Active from End-of-Write
t
CHZ
Write Cycle
t
WHZ(1)
Write Enable to Output in High-Z
NOTES
1. This parameter is guaranteed by design, but not tested.
2. t
AS
=0ns for
CS
controlled write cycles
.
t
DH
, t
WR
= 3ns for
CS
controlled write cycles.
7.11
2675 tbl 10
3
IDT7MB4048
512K x 8 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1
(1)
t
RC
ADDRESS
t
AA
OE
t
OE
t
OH
CS
t
OLZ
t
CLZ
(5)
(5)
t
ACS
t
CHZ
(5)
t
OHZ
(5)
DATA
OUT
2675 drw 06
TIMING WAVEFORM OF READ CYCLE NO. 2
(1, 2, 4)
t
RC
ADDRESS
t
AA
t
OH
DATA
OUT
t
OH
2675 drw 07
TIMING WAVEFORM OF READ CYCLE NO. 3
(1, 3, 4)
CS
t
ACS
t
CLZ
DATA
OUT
(5)
t
CHZ
(5)
2675 drw 08
NOTES:
1.
WE
is HIGH for Read Cycle.
2. Device is continuously selected,
CS
= V
IL
.
3. Address valid prior to or coincident with
CS
transition LOW.
4.
OE
= V
IL
.
5. Transition is measured
±200mV
from steady state. This parameter is guaranteed by design, but not tested.
7.11
4
IDT7MB4048
512K x 8 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
WE
CONTROLLED TIMING)
(1, 2, 3, 7)
t
WC
ADDRESS
OE
t
AW
CS
t
AS
t
WP
(7)
t
WR
WE
t
WHZ
t
OHZ
DATA
OUT
(4)
(6)
(6)
t
OHZ
t
OW (6)
(4)
(6)
t
DH
t
DW
DATA
IN
DATA VALID
2675 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
CS
CONTROLLED TIMING)
(1, 2, 3, 5)
t
WC
ADDRESS
t
AW
CS
t
AS
t
CW
t
WR
WE
t
DW
DATA
IN
DATA VALID
2675 drw 10
t
DH
NOTES:
1.
WE
or
CS
must be HIGH during all address transitions.
2. A write occurs during the overlap (t
WP
) of a LOW
CS
and a LOW
WE
.
3. t
WR
is measured from the earlier of
CS
or
WE
going HIGH to the end of write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the
CS
LOW transition occurs simultaneously with or after the
WE
LOW transition, the outputs remain in a high-impedance state.
6. Transition is measured
±200mV
from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but not tested.
7. If
OE
is LOW during a
WE
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WHZ
+ t
DW
) to allow the I/O drivers to turn off and data
to be placed on the bus for the required t
DW
. If
OE
is HIGH during a
WE
controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified t
WP
.
7.11
5
