OCTAL CHANNEL T1/E1/J1
SHORT HAUL LINE INTERFACE UNIT
IDT82V2048E
FEATURES:
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Eight channel T1/E1/J1 short haul line interfaces
Supports HPS (Hitless Protection Switching) for 1+1 protection
without external relays
Programmable T1/E1/J1 switchability allowing one bill of ma-
terial for any line condition
Single 3.3 V power supply with 5 V tolerance on digital interfaces
Meets or exceeds specifications in
-
ANSI T1.102, T1.403 and T1.408
- ITU I.431, G.703,G.736, G.775 and G.823
- ETSI 300-166, 300-233 and TBR 12/13
- AT&T Pub 62411
Per channel software selectable on:
- Wave-shaping templates
- Line terminating impedance (T1:100
Ω,
J1:110
Ω,
E1:75
Ω/120 Ω)
- Adjustment of arbitrary pulse shape
- JA (Jitter Attenuator) position (receive path or transmit path)
- Single rail/dual rail system interfaces
-
B8ZS/HDB3/AMI line encoding/decoding
- Active edge of transmit clock (TCLK) and receive clock (RCLK)
- Active level of transmit data (TDATA) and receive data (RDATA)
- Receiver or transmitter power down
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- High impedance setting for line drivers
- PRBS (Pseudo Random Bit Sequence) generation and detection
with 2
15
-1 PRBS polynomials for E1
- QRSS (Quasi Random Sequence Signals) generation and detection
with 2
20
-1 QRSS polynomials for T1/J1
- 16-bit BPV (Bipolar Pulse Violation)/Excess Zero/PRBS or QRSS
error counter
- Analog loopback, Digital loopback, Remote loopback and Inband
loopback
Adaptive receive sensitivity up to -20 dB
Non-intrusive monitoring per ITU G.772 specification
Short circuit protection for line drivers
LOS (Loss Of Signal) detection with programmable LOS levels
AIS (Alarm Indication Signal) detection
JTAG interface
Supports serial control interface, Motorola and Intel Non-Multi-
plexed interfaces
Package:
IDT82V2048E: 208-pin PQFP and 208-pin PBGA
DESCRIPTION:
The IDT82V2048E can be configured as an octal T1, octal E1 or octal
J1 Line Interface Unit. The IDT82V2048E performs clock/data recovery,
AMI/B8ZS/HDB3 line decoding and detects and reports the LOS condi-
tions. An integrated Adaptive Equalizer is available to increase the receive
sensitivity and enable programming of LOS levels. In transmit path, there
is an AMI/B8ZS/HDB3 encoder and Waveform Shaper. There is one Jitter
Attenuator for each channel, which can be placed in either the receive path
or the transmit path. The Jitter Attenuator can also be disabled. The
IDT82V2048E supports both Single Rail and Dual Rail system interfaces
and both serial and parallel control interfaces. To facilitate the network
maintenance, a PRBS/QRSS generation/detection circuit is integrated in
each channel, and different types of loopbacks can be set on a per channel
basis. Four different kinds of line terminating impedance, 75Ω, 100
Ω,
110
Ω
and 120
Ω
are selectable on a per channel basis. The chip also provides
driver short-circuit protection and supports JTAG boundary scanning.
The IDT82V2048E can be used in SDH/SONET, LAN, WAN, Routers,
Wireless Base Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay
Access Devices, CSU/DSU equipment, etc.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGES
1
August 2004
DSC-6532/-
2003 Integrated Device Technology, Inc. All rights reserved.
One of the Eight Identical Channels
LOSn
LOS/AIS
Detector
RTIPn
RRINGn
FUNCTIONAL BLOCK DIAGRAM
RCLKn
RDn/RDPn
CVn/RDNn
Jitter
Attenuator
Data
Slicer
Adaptive
Equalizer
B8ZS/
HDB3/AMI
Decoder
Clock and
Data
Recovery
Receiver
Internal
Termination
PRBS Detector
IBLC Detector
Remote
Loopback
Digital
Loopback
Analog
Loopback
TTIPn
TRINGn
OCTAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
Figure-1 Block Diagram
2
Microprocessor
Interface
Basic
Control
JTAG TAP
RST
REF
THZ
TDO
TDI
TMS
TCK
TRST
TCLKn
TDn/TDPn
TDNn
Jitter
Attenuator
Line
Driver
Waveform
Shaper
B8ZS/
HDB3/AMI
Encoder
Transmitter
Internal
Termination
PRBS Generator
IBLC Generator
TAOS
Clock
Generator
VDDD
VDDIO
VDDA
VDDT
VDDR
G.772
Monitor
SCLKE
INT/MOT
P/S
A[7:0]
D[7:0]
INT
SDO
SDI/R/W/WR
DS/RD
SCLK
CS
MCLK
MCLKS
INDUSTRIAL
TEMPERATURE RANGES
OCTAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL
TEMPERATURE RANGES
TABLE OF CONTENTS
1
2
3
IDT82V2048E PIN CONFIGURATIONS ....................................................................................... 8
PIN DESCRIPTION ..................................................................................................................... 10
FUNCTIONAL DESCRIPTION .................................................................................................... 16
3.1
T1/E1/J1 MODE SELECTION .......................................................................................... 16
3.2
TRANSMIT PATH ............................................................................................................. 16
3.2.1 TRANSMIT PATH SYSTEM INTERFACE.............................................................. 16
3.2.2 ENCODER .............................................................................................................. 16
3.2.3 PULSE SHAPER .................................................................................................... 16
3.2.3.1 Preset Pulse Templates .......................................................................... 16
3.2.3.2 User-Programmable Arbitrary Waveform ................................................ 17
3.2.4 TRANSMIT PATH LINE INTERFACE..................................................................... 20
3.2.5 TRANSMIT PATH POWER DOWN ........................................................................ 20
3.3
RECEIVE PATH ............................................................................................................... 21
3.3.1 RECEIVE INTERNAL TERMINATION.................................................................... 21
3.3.2 LINE MONITOR ...................................................................................................... 22
3.3.3 ADAPTIVE EQUALIZER......................................................................................... 22
3.3.4 RECEIVE SENSITIVITY ......................................................................................... 22
3.3.5 DATA SLICER ........................................................................................................ 22
3.3.6 CDR (Clock & Data Recovery)................................................................................ 22
3.3.7 DECODER .............................................................................................................. 22
3.3.8 RECEIVE PATH SYSTEM INTERFACE ................................................................ 22
3.3.9 RECEIVE PATH POWER DOWN........................................................................... 22
3.3.10 G.772 NON-INTRUSIVE MONITORING ................................................................ 23
3.4
JITTER ATTENUATOR .................................................................................................... 24
3.4.1 JITTER ATTENUATION FUNCTION DESCRIPTION ............................................ 24
3.4.2 JITTER ATTENUATOR PERFORMANCE ............................................................. 24
3.5
LOS AND AIS DETECTION ............................................................................................. 25
3.5.1 LOS DETECTION ................................................................................................... 25
3.5.2 AIS DETECTION .................................................................................................... 26
3.6
TRANSMIT AND DETECT INTERNAL PATTERNS ........................................................ 27
3.6.1 TRANSMIT ALL ONES ........................................................................................... 27
3.6.2 TRANSMIT ALL ZEROS......................................................................................... 27
3.6.3 PRBS/QRSS GENERATION AND DETECTION.................................................... 27
3.7
LOOPBACK ...................................................................................................................... 27
3.7.1 ANALOG LOOPBACK ............................................................................................ 27
3.7.2 DIGITAL LOOPBACK ............................................................................................. 27
3.7.3 REMOTE LOOPBACK............................................................................................ 27
3.7.4 INBAND LOOPBACK.............................................................................................. 29
3.7.4.1 Transmit Activate/Deactivate Loopback Code......................................... 29
3.7.4.2 Receive Activate/Deactivate Loopback Code.......................................... 29
3.7.4.3 Automatic Remote Loopback .................................................................. 29
3.8
ERROR DETECTION/COUNTING AND INSERTION ...................................................... 30
3
OCTAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL
TEMPERATURE RANGES
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
4
3.8.1 DEFINITION OF LINE CODING ERROR ............................................................... 30
3.8.2 ERROR DETECTION AND COUNTING ................................................................ 30
3.8.3 BIPOLAR VIOLATION AND PRBS ERROR INSERTION ...................................... 31
LINE DRIVER FAILURE MONITORING ........................................................................... 31
MCLK AND TCLK ............................................................................................................. 32
3.10.1 MASTER CLOCK (MCLK) ...................................................................................... 32
3.10.2 TRANSMIT CLOCK (TCLK).................................................................................... 32
MICROCONTROLLER INTERFACES ............................................................................. 33
3.11.1 PARALLEL MICROCONTROLLER INTERFACE................................................... 33
3.11.2 SERIAL MICROCONTROLLER INTERFACE ........................................................ 33
INTERRUPT HANDLING .................................................................................................. 34
GENERAL PURPOSE I/O ................................................................................................ 35
5V TOLERANT I/O PINS .................................................................................................. 35
RESET OPERATION ........................................................................................................ 35
POWER SUPPLY ............................................................................................................. 35
PROGRAMMING INFORMATION .............................................................................................. 36
4.1
REGISTER LIST AND MAP ............................................................................................. 36
4.2
REGISTER DESCRIPTION .............................................................................................. 38
4.2.1 GLOBAL REGISTERS............................................................................................ 38
4.2.2 JITTER ATTENUATION CONTROL REGISTER ................................................... 40
4.2.3 TRANSMIT PATH CONTROL REGISTERS........................................................... 41
4.2.4 RECEIVE PATH CONTROL REGISTERS ............................................................. 43
4.2.5 NETWORK DIAGNOSTICS CONTROL REGISTERS ........................................... 45
4.2.6 INTERRUPT CONTROL REGISTERS ................................................................... 48
4.2.7 LINE STATUS REGISTERS ................................................................................... 50
4.2.8 INTERRUPT STATUS REGISTERS ...................................................................... 52
4.2.9 COUNTER REGISTERS ........................................................................................ 53
4.2.10 TRANSMIT AND RECEIVE TERMINATION REGISTER ....................................... 54
IEEE STD 1149.1 JTAG TEST ACCESS PORT ........................................................................ 55
5.1
JTAG INSTRUCTIONS AND INSTRUCTION REGISTER ............................................... 56
5.2
JTAG DATA REGISTER ................................................................................................... 56
5.2.1 DEVICE IDENTIFICATION REGISTER (IDR) ........................................................ 56
5.2.2 BYPASS REGISTER (BR)...................................................................................... 56
5.2.3 BOUNDARY SCAN REGISTER (BSR) .................................................................. 56
5.2.4 TEST ACCESS PORT CONTROLLER .................................................................. 57
TEST SPECIFICATIONS ............................................................................................................ 59
MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS ......................................... 71
7.1
SERIAL INTERFACE TIMING .......................................................................................... 71
7.2
PARALLEL INTERFACE TIMING ..................................................................................... 72
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4
OCTAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL
TEMPERATURE RANGES
LIST OF TABLES
Table-1
Table-2
Table-3
Table-4
Table-5
Table-6
Table-7
Table-8
Table-9
Table-10
Table-11
Table-12
Table-13
Table-14
Table-15
Table-16
Table-17
Table-18
Table-19
Table-20
Table-21
Table-22
Table-23
Table-24
Table-25
Table-26
Table-27
Table-28
Table-29
Table-30
Table-31
Table-32
Table-33
Table-34
Table-35
Table-36
Table-37
Table-38
Table-39
Table-40
Pin Description ..............................................................................................................
Transmit Waveform Value For E1 75
Ω
........................................................................
Transmit Waveform Value For E1 120
Ω
......................................................................
Transmit Waveform Value For T1 0~133 ft...................................................................
Transmit Waveform Value For T1 133~266 ft...............................................................
Transmit Waveform Value For T1 266~399 ft...............................................................
Transmit Waveform Value For T1 399~533 ft...............................................................
Transmit Waveform Value For T1 533~655 ft...............................................................
Transmit Waveform Value For J1 0~655 ft ...................................................................
Impedance Matching for Transmitter ............................................................................
Impedance Matching for Receiver ................................................................................
Criteria of Starting Speed Adjustment...........................................................................
LOS Declare and Clear Criteria, Adaptive Equalizer Disabled .....................................
LOS Declare and Clear Criteria, Adaptive Equalizer Enabled ......................................
AIS Condition ................................................................................................................
Criteria for Setting/Clearing the PRBS_S Bit ................................................................
EXZ Definition ...............................................................................................................
Interrupt Event...............................................................................................................
Global Register List and Map........................................................................................
Per Channel Register List and Map ..............................................................................
ID: Chip Revision Register ............................................................................................
RST: Reset Register .....................................................................................................
GCF0: Global Configuration Register 0 ........................................................................
GCF1: Global Configuration Register 1 ........................................................................
INTCH: Interrupt Channel Indication Register...............................................................
GPIO: General Purpose IO Pin Definition Register.......................................................
JACF: Jitter Attenuator Configuration Register .............................................................
TCF0: Transmitter Configuration Register 0 .................................................................
TCF1: Transmitter Configuration Register 1 .................................................................
TCF2: Transmitter Configuration Register 2 .................................................................
TCF3: Transmitter Configuration Register 3 .................................................................
TCF4: Transmitter Configuration Register 4 .................................................................
RCF0: Receiver Configuration Register 0.....................................................................
RCF1: Receiver Configuration Register 1.....................................................................
RCF2: Receiver Configuration Register 2.....................................................................
MAINT0: Maintenance Function Control Register 0......................................................
MAINT1: Maintenance Function Control Register 1......................................................
MAINT2: Maintenance Function Control Register 2......................................................
MAINT3: Maintenance Function Control Register 3......................................................
MAINT4: Maintenance Function Control Register 4......................................................
5
10
17
18
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19
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19
20
21
24
25
26
26
27
30
34
36
37
38
38
38
39
39
39
40
41
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42
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43
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