ADC1215S series
Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps
with input buffer; CMOS or LVDS DDR digital outputs
Rev. 03 — 2 July 2012
Product data sheet
1. General description
The ADC1215S is a single channel 12-bit Analog-to-Digital Converter (ADC) optimized for
high dynamic performance and low power consumption at sample rates up to 125 Msps.
Pipelined architecture and output error correction ensure the ADC1215S is accurate
enough to guarantee zero missing codes over the entire operating range. Supplied from a
single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode
because of a separate digital output supply.
The ADC1215S supports the Low Voltage Differential Signalling (LVDS) Double Data
Rate (DDR) output standard. An integrated Serial Peripheral Interface (SPI) allows the
user to easily configure the ADC.
The device also includes a SPI programmable full-scale to allow flexible input voltage
range from 1 V to 2 V (peak-to-peak). With excellent dynamic performance from the
baseband to input frequencies of 170 MHz or more, the ADC1215S is ideal for use in
communications, imaging and medical applications - especially in high Intermediate
Frequency (IF) applications because of the integrated input buffer. The input buffer
ensures that the input impedance remains constant and low and the performance
consistent over a wide frequency range.
2. Features and benefits
SNR, 70 dBFS / SFDR, 86 dBc
Sample rate up to 125 Msps
12-bit pipelined ADC core
Clock input divided by 2 for less jitter
contribution
Integrated input buffer
Flexible input voltage range: 1 V (p-p) to
2 V (p-p)
CMOS or LVDS DDR digital outputs
Pin compatible with the ADC1415S
series, the ADC1015S series and the
ADC1115S125
Input bandwidth, 600 MHz
Power dissipation, 635 mW at 80 Msps,
including analog input buffer
SPI
Duty cycle stabilizer
Fast OuT-of-Range (OTR) detection
Offset binary, two’s complement, gray
code
Power-down and Sleep modes
HVQFN40 package
®
Integrated Device Technology
ADC1215S series
Single 12-bit ADC; input buffer; CMOS or LVDS DDR digital output
3. Applications
Wireless and wired broadband
communications
Portable instrumentation
Imaging systems
Digital predistortion loop, power
amplifier linearization
Spectral analysis
Ultrasound equipment
Software defined radio
4. Ordering information
Table 1.
Ordering information
f
s
(Msps) Package
Name
ADC1215S125HN-C1 125
ADC1215S105HN-C1 105
ADC1215S080HN-C1 80
ADC1215S065HN-C1 65
Description
Version
SOT618-6
SOT618-6
SOT618-6
SOT618-6
HVQFN40 plastic thermal enhanced very thin quad flat package; no
leads; 40 terminals; body 6
6
0.85 mm
HVQFN40 plastic thermal enhanced very thin quad flat package; no
leads; 40 terminals; body 6
6
0.85 mm
HVQFN40 plastic thermal enhanced very thin quad flat package; no
leads; 40 terminals; body 6
6
0.85 mm
HVQFN40 plastic thermal enhanced very thin quad flat package; no
leads; 40 terminals; body 6
6
0.85 mm
Type number
ADC1215S_SER 3
© IDT All rights reserved.
Product data sheet
Rev. 03 — 2 July 2012
2 of 40
Integrated Device Technology
ADC1215S series
Single 12-bit ADC; input buffer; CMOS or LVDS DDR digital output
5. Block diagram
SDIO/ODS
CS
SCLK/DFS
ADC1215S
ERROR
CORRECTION AND
DIGITAL
PROCESSING
SPI
OTR
CMOS:
D11 to D0
or
LVDS DDR:
D10_D11_P
to D0_D1_P
D10_D11_M
to D0_D1_M
CMOS:
DAV
or
LVDS DDR:
DAVP
DAVM
INP
INPUT
BUFFER
INM
S/H
INPUT
STAGE
ADC CORE
12-BIT
PIPELINED
OUTPUT
DRIVERS
OUTPUT
DRIVERS
CLOCK INPUT
STAGE AND DUTY
CYCLE CONTROL
SYSTEM
REFERENCE AND
POWER
MANAGEMENT
PWD
OE
CLKP CLKM
VREF
REFB
VCM
SENSE REFT
005aaa140
Fig 1.
Block diagram
ADC1215S_SER 3
© IDT All rights reserved.
Product data sheet
Rev. 03 — 2 July 2012
3 of 40
Integrated Device Technology
ADC1215S series
Single 12-bit ADC; input buffer; CMOS or LVDS DDR digital output
6. Pinning information
6.1 Pinning
36 SCLK/DFS
37 SDIO/ODS
36 SCLK/DFS
37 SDIO/ODS
39 SENSE
34 OGND
33 VDDO
40 VREF
35 OTR
39 SENSE
34 OGND
33 VDDO
40 VREF
35 OTR
38 CS
terminal 1
index area
REFB
REFT
AGND
VCM
VDDA5V
AGND
INM
INP
AGND
1
2
3
4
5
6
7
8
9
31 DAV
32 n.c.
REFB
30 n.c.
29 n.c.
28 D0
27 D1
26 D2
25 D3
24 D4
23 D5
22 D6
21 D7
REFT
AGND
VCM
VDDA5V
AGND
INM
INP
AGND
1
2
3
4
5
6
7
8
9
38 CS
terminal 1
index area
31 DAV
30 n.c.
29 n.c.
28 D0_D1_P
27 D0_D1_M
26 D2_D3_P
25 D2_D3_M
24 D4_D5_P
23 D4_D5_M
22 D6_D7_P
21 D6_D7_M
D8_D9_P 20
005aaa142
© IDT All rights reserved.
ADC1215S
HVQFN40
ADC1215S
HVQFN40
VDDA3V 10
VDDA3V 11
CLKP 12
CLKM 13
DEC 14
OE 15
PWD 16
D10_D11_M 17
D10_D11_P 18
D8_D9_M 19
VDDA3V 10
VDDA3V 11
CLKP 12
CLKM 13
DEC 14
OE 15
PWD 16
D11 17
D10 18
D9 19
D8 20
005aaa141
Transparent top view
Transparent top view
Fig 2.
Pin configuration with CMOS digital outputs
selected
Fig 3.
Pin configuration with LVDS/DDR digital
outputs selected
6.2 Pin description
Table 2.
Symbol
REFB
REFT
AGND
VCM
VDDA5V
AGND
INM
INP
AGND
VDDA3V
VDDA3V
CLKP
CLKM
DEC
OE
PWD
ADC1215S_SER 3
Pin description (CMOS digital outputs)
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Type
[1]
O
O
G
O
P
G
I
I
G
P
P
I
I
O
I
I
Description
bottom reference
top reference
analog ground
common-mode output voltage
5 V analog power supply
analog ground
complementary analog input
analog input
analog ground
3 V analog power supply
3 V analog power supply
clock input
complementary clock input
regulator decoupling node
output enable, active LOW
power down, active HIGH
Product data sheet
Rev. 03 — 2 July 2012
32 n.c.
4 of 40
Integrated Device Technology
ADC1215S series
Single 12-bit ADC; input buffer; CMOS or LVDS DDR digital output
Table 2.
Symbol
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
n.c.
n.c.
DAV
n.c.
VDDO
OGND
OTR
SCLK/DFS
SDIO/ODS
CS
SENSE
VREF
[1]
Pin description (CMOS digital outputs)
…continued
Pin
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Type
[1]
O
O
O
O
O
O
O
O
O
O
O
O
-
-
O
-
P
G
O
I
I/O
I
I
I/O
Description
data output bit 11 (Most Significant Bit (MSB))
data output bit 10
data output bit 9
data output bit 8
data output bit 7
data output bit 6
data output bit 5
data output bit 4
data output bit 3
data output bit 2
data output bit 1
data output bit 0 (Least Significant Bit (LSB))
not connected
not connected
data valid output clock
not connected
output power supply
output ground
out of range
SPI clock / data format select
SPI data IO / output data standard
SPI chip select
reference programming pin
voltage reference input/output
P: power supply; G: ground; I: input; O: output; I/O: input/output.
Table 3.
Symbol
Pin description (LVDS/DDR) digital outputs)
Pin
[1]
17
18
19
20
21
22
23
24
25
26
27
28
29
Type
[2]
O
O
O
O
O
O
O
O
O
O
O
O
-
Description
differential output data D10 and D11 multiplexed, complement
differential output data D10 and D11 multiplexed, true
differential output data D8 and D9 multiplexed, complement
differential output data D8 and D9 multiplexed, true
differential output data D6 and D7 multiplexed, complement
differential output data D6 and D7 multiplexed, true
differential output data D4 and D5 multiplexed, complement
differential output data D4 and D5 multiplexed, true
differential output data D2 and D3 multiplexed, complement
differential output data D2 and D3 multiplexed, true
differential output data D0 and D1 multiplexed, complement
differential output data D0 and D1 multiplexed, true
not connected
D10_D11_M
D10_D11_P
D8_D9_M
D8_D9_P
D6_D7_M
D6_D7_P
D4_D5_M
D4_D5_P
D2_D3_M
D2_D3_P
D0_D1_M
D0_D1_P
n.c.
ADC1215S_SER 3
© IDT All rights reserved.
Product data sheet
Rev. 03 — 2 July 2012
5 of 40
