IMI4345
PRODUCT DESCRIPTION
The IMI4345 is one of the family of LSI PLL frequency
synthesizer IC’s offered by International Microcircuits.
The device is a very fast CMOS digital phase/frequency
detector. It compares two input signals and produces an
output error signal linearly proportional to the phase
difference. When used with a prescaler, a loop filter,
and a VCO; the IMI4345 can create a very broad
bandwidth frequency synthesizer.
PHASE DETECTOR
CMOS LSI
PRODUCT FEATURES
HIGH SPEED PHASE DETECTOR
-
PLL FREQUENCY SYNTHESIZERS
Approved Product
APPLICATIONS
This device can be used in general applications which
require high performance phase detection such as:
CATV, AM/FM Radio, TV Tuning and Scanning
Receivers.
With its exceptional bandwidth it can also be used in
Radar and Video applications.
T
T
T
T
T
T
T
T
T
T
> 40 MHz typical operating frequency
5 ns typical pulse width
TTL level compatibility
Linear digital phase detection
4.5 to 5.5 volt Operating Range
Single-ended or Doubled-ended outputs
Lock detect signal
Suitable for systems requiring ZERO phase-
difference at lock
Low power consumption
Packaging options include:
- Plastic and Ceramic Dual-in-line
- SOIC
BLOCK DIAGRAM
Charge
Pump
8
7
PDout
Refin
1
1
2
1
2
6
Fin
VSS
2
4
Phase Freq.
Detector
1
2
1
2
PHIR
PHIV
Lock
5
3
NOTE: Internal feedback resistors have been deleted. See page 5 for details.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571
Rev 1.3
12/16/97
Page 1 of 8
IMI4345
PHASE DETECTOR
CMOS LSI
MAXIMUM RATINGS
HIGH SPEED PHASE DETECTOR
-
PLL FREQUENCY SYNTHESIZERS
Approved Product
Voltage Relative to VSS:
Voltage Relative to VDD:
Storage Temperature:
Ambient Temperature:
Recommend Operating Range:
-0.3V to 5.5V
0.3V
-65°C to 150°C
-40°C to 85°C
4.5 - 5.5V
This device contains circuitry to protect the inputs from
damage due to high static voltages or electric fields;
however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)< VDD
Maximum ratings are conditions beyond which damage
to the device may occur (voltage referenced to V
SS
).
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
PIN DESCRIPTIONS
PIN #
1
2
4
8
6
5
7
NAME
REFin
Fin
Vss
Vdd
PHIR
PHIV
Pdout
DESCRIPTION
This input is self biased and is designed to be AC coupled for low level sinewave signals.
This input is self biased and is designed to be AC coupled for low level sinewave signals. For
CMOS logic level input signals, DC coupling can be used.
Circuit ground.
Circuit positive power supply.
Phase detector output. This signal goes LOW when the Fin is less than Fref.
Phase detector output. This signal goes LOW when the Fin is greater than Fref.
Single-ended charge pump output, usually used with passive loop filters. This signal operates
according to the following:
þ
þ
þ
3
Lock
Frequency fv>fr at the phase detector: negative pulses.
Frequency fv<fr at the phase detector: positive pulses.
Frequency fv = fr at the phase detector: high-impedance state.
Lock detect output. When the PLL is locked, this signal will be essentially HIGH, with very narrow
negative spikes at the phase detection frequency. If the PLL is out of lock, this signal will pulse
LOW.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571
Page 2 of 8
12/16/97
Rev 1.3
IMI4345
PHASE DETECTOR
CMOS LSI
HIGH SPEED PHASE DETECTOR
-
PLL FREQUENCY SYNTHESIZERS
Approved Product
SWITCHING CHARACTERICS
Characteristics
Output Rise and Fall Time
Output Pulse Width PHIR. PHIV with f
R
in
phase with f
V
Positive Clock Pulse Width
Negative Clock Pulse Width
Maximum Frequency
T
A
= -55 to + 125°C
V
DD
= 4.5 to 5.5V
C
L
= 50pF
Symbol
t
R
, t
F
t
WO
t
WP
t
WN
f
MAX
Min.
-
0
8
8
40
Typ.
10
5
5
5
60
Max.
20
8
-
-
-
Units
ns
ns
ns
ns
MHz
ELECTRICAL CHARACTERISTICS
Characteristics
Input Voltage
V
O
= 0.4 or 2.4 V
Output Current PHIR, PHIV & LD only
V
OH
= 2.4V
V
OL
= 0.4V
Charge Pump Current only
PD
OUT
3-State Leakage
Input Capacitance
Input Capacitance
Quiescent Current
Dynamic Current at 20 MHz
Symbol
V
IL
V
IH
I
OH
I
OH
I
OL
I
CP
I
L
C
IN
C
OUT
IDD
st
IDD
dyn
2.2
6.0
6.0
3.0
±80
-55 to 125°C
4.5 to 5.5V
Min.
Max.
0.8
2.0
7.0
7.0
3.5
±90
-40 to 85°C
4.75 to 5.25V
Min.
Max.
0.8
25°C
5V
Typ.
1.2
1.6
8
8
4
±130
±0.1
3
5
350
30
Units
V
dc
mA
mA
mA
uA
uA
pF
pF
uA
mA
±235
±1
6
8
500
50
±230
±0.5
6
8
500
50
IDD
st
= IDD in static conditions: All inputs tied low, - No output loading
IDD
dyn
= IDD dynamic conditions: fr = fv = 20 Mhz - No output loading
I
CP
= Charge Pump Current
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571
Rev 1.3
12/16/97
Page 3 of 8
IMI4345
PHASE DETECTOR
CMOS LSI
HIGH SPEED PHASE DETECTOR
-
PLL FREQUENCY SYNTHESIZERS
Approved Product
PIN ASSIGNMENT
F
R
F
V
LD
V
SS
1
2
3
4
8 V
DD
7 PD
OUT
6
5
PHIR
PHIV
PHASE DETECTOR OUTPUT WAVEFORMS
F
R
F
V
PDout
PHIR
PHIV
LD
NOTE: The PD
OUT
state is equal to either V
DD
or V
SS
when active. When not active, the output is high impedance and
the voltage at that pin is determined by the low pass filter capacitor.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571
Page 4 of 8
12/16/97
Rev 1.3
IMI4345
PHASE DETECTOR
CMOS LSI
AC COUPLING FOR FIN AND REFIN
VDD
.01
REFIN
20
k
Pin #1
20
k
VDD
.01
FIN
20
k
20
k
HIGH SPEED PHASE DETECTOR
-
PLL FREQUENCY SYNTHESIZERS
Approved Product
Pin #2
PHASE LOCKED LOOP - LOW PASS FILTER DESIGN
Figure A)
C2
R2
C1
Figure B)
PD
OUT
v
OUT
PHIR
R1
R2
C1
C2
PHIV
R1
A
VC
R2
C2
C1
Refer to Note 1
K∅K
VCO
NCR
1
ωN
R
2
C
2
R
2
CS +1
2
ωN
=
εN=
Assuming gain A is very large, then: F(S) =
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571
Rev 1.3
12/16/97
Page 5 of 8
