PD - 91644A
IRL1004S
IRL1004L
Logic-Level Gate Drive
l
Advanced Process Technology
l
Ultra Low On-Resistance
l
Dynamic dv/dt Rating
l
175°C Operating Temperature
l
Fast Switching
l
Fully Avalanche Rated
Description
l
HEXFET
®
Power MOSFET
D
V
DSS
= 40V
G
S
R
DS(on)
= 0.0065Ω
I
D
= 130A
Fifth Generation HEXFET
®
power MOSFETs from
International Rectifier utilize advanced processing
techniques to achieve extremely low on-resistance per
silicon area. This benefit, combined with the fast switching
speed and ruggedized device design that HEXFET power
MOSFETs are well known for, provides the designer with
an extremely efficient and reliable device for use in a wide
variety of applications.
The D
2
Pak is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible on-
resistance in any existing surface mount package. The
D
2
Pak is suitable for high current applications because of
its low internal connection resistance and can dissipate
up to 2.0W in a typical surface mount application.
The through-hole version (IRL1004L) is available for low-
profile application.
D
2
Pak
IRL1004S
TO-262
IRL1004L
Absolute Maximum Ratings
Parameter
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
DM
P
D
@T
A
= 25°C
P
D
@T
C
= 25°C
V
GS
E
AS
I
AR
E
AR
dv/dt
T
J
T
STG
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
Power Dissipation
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Max.
130
92
520
3.8
200
1.3
± 16
700
78
20
5.0
-55 to + 175
300 (1.6mm from case)
Units
A
W
W
W/°C
V
mJ
A
mJ
V/ns
°C
Thermal Resistance
Parameter
R
θJC
R
θJA
Junction-to-Case
Junction-to-Ambient ( PCB Mounted,steady-state)*
Typ.
–––
–––
Max.
0.75
40
Units
°C/W
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1
12/29/99
IRL1004S/1004L
Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
V
(BR)DSS
∆V
(BR)DSS
/∆T
J
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Internal Source Inductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
R
DS(on)
V
GS(th)
g
fs
I
DSS
I
GSS
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
L
S
C
iss
C
oss
C
rss
Min.
40
–––
–––
–––
1.0
63
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ. Max. Units
Conditions
––– –––
V
V
GS
= 0V, I
D
= 250µA
0.04 ––– V/°C Reference to 25°C, I
D
= 1mA
––– 0.0065
V
GS
= 10V, I
D
= 78A
Ω
––– 0.009
V
GS
= 4.5V, I
D
= 65A
–––
V
V
DS
= V
GS
, I
D
= 250µA
––– –––
S
V
DS
= 25V, I
D
= 78A
––– 25
V
DS
= 40V, V
GS
= 0V
µA
––– 250
V
DS
= 32V, V
GS
= 0V, T
J
= 150°C
––– 100
V
GS
= 16V
nA
––– -100
V
GS
= -16V
––– 100
I
D
= 78A
––– 32
nC
V
DS
= 32V
––– 43
V
GS
= 4.5V, See Fig. 6 and 13
16 –––
V
DD
= 20V,
210 –––
I
D
= 78A,
25 –––
ns
R
G
= 2.5Ω,
14 –––
R
D
= 0.18Ω, See Fig. 10
Between lead,
7.5
nH
–––
and center of die contact
5330 –––
V
GS
= 0V
1480 –––
pF
V
DS
= 25V
320 –––
ƒ = 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
I
S
I
SM
V
SD
t
rr
Q
rr
t
on
Notes:
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
––– ––– 130
showing the
A
G
integral reverse
––– ––– 520
S
p-n junction diode.
––– ––– 1.3
V
T
J
= 25°C, I
S
= 78A, V
GS
= 0V
––– 78 120
ns
T
J
= 25°C, I
F
= 78A
––– 180 270
nC di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
+L
D
)
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11)
Pulse width
≤
300µs; duty cycle
≤
2%.
Calculated continuous current based on maximum allowable
junction temperature; for recommended current-handing of the
package refer to Design Tip # 93-4
Uses IRL1004 data and test conditions
Starting T
J
= 25°C, L = 0.23mH
R
G
= 25Ω, I
AS
= 78A. (See Figure 12)
I
SD
≤
78A, di/dt
≤
370A/µs, V
DD
≤
V
(BR)DSS
,
T
J
≤
175°C
* When mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
2
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IRL1004S/1004L
10000
VGS
15V
10V
7.0V
5.5V
4.5V
4.0V
3.5V
BOTTOM 2.7V
TOP
1000
I
D
, Drain-to-Source Current (A)
1000
100
10
I
D
, Drain-to-Source Current (A)
VGS
15V
10V
7.0V
5.5V
4.5V
4.0V
3.5V
BOTTOM 2.7V
TOP
100
10
2.7V
1
2.7V
20µs PULSE WIDTH
T
J
= 25
°
C
1
10
100
0.1
0.1
1
0.1
20µs PULSE WIDTH
T
J
= 175
°
C
1
10
100
V
DS
, Drain-to-Source Voltage (V)
V
DS
, Drain-to-Source Voltage (V)
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
1000
2.5
I
D
= 130A
T
J
= 25
°
C
R
DS(on)
, Drain-to-Source On Resistance
(Normalized)
I
D
, Drain-to-Source Current (A)
2.0
100
T
J
= 175
°
C
1.5
10
1.0
1
0.5
0.1
2.0
V DS = 50V
20µs PULSE WIDTH
3.0
4.0
5.0
6.0
7.0
8.0
9.0
0.0
-60 -40 -20
V
GS
= 10V
0
20 40 60 80 100 120 140 160 180
V
GS
, Gate-to-Source Voltage (V)
T
J
, Junction Temperature (
°
C)
Fig 3.
Typical Transfer Characteristics
Fig 4.
Normalized On-Resistance
Vs. Temperature
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3
IRL1004S/1004L
10000
V
GS
, Gate-to-Source Voltage (V)
8000
V
GS
= 0V,
f = 1MHz
C
iss
= C
gs
+ C
gd ,
C
ds
SHORTED
C
rss
= C
gd
C
oss
= C
ds
+ C
gd
12
I
D
= 78 A
V
DS
= 32V
V
DS
= 20V
10
C, Capacitance (pF)
6000
C
iss
8
6
4000
C
oss
4
2000
C
rss
0
1
10
100
2
0
0
30
60
90
FOR TEST CIRCUIT
SEE FIGURE 13
120
150
180
V
DS
, Drain-to-Source Voltage (V)
Q
G
, Total Gate Charge (nC)
Fig 5.
Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 6.
Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
10000
I
SD
, Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
T
J
= 175
°
C
1000
10us
100
I
D
, Drain Current (A)
10
100
100us
1ms
T
J
= 25
°
C
1
10
10ms
0.1
0.0
V
GS
= 0 V
0.5
1.0
1.5
2.0
2.5
3.0
1
1
T
C
= 25 °C
T
J
= 175 °C
Single Pulse
10
100
V
SD
,Source-to-Drain Voltage (V)
V
DS
, Drain-to-Source Voltage (V)
Fig 7.
Typical Source-Drain Diode
Forward Voltage
Fig 8.
Maximum Safe Operating Area
4
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IRL1004S/1004L
140
LIMITED BY PACKAGE
120
V
DS
V
GS
R
G
R
D
D.U.T.
+
I
D
, Drain Current (A)
100
-
V
DD
80
10V
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
60
40
Fig 10a.
Switching Time Test Circuit
V
DS
20
90%
0
25
50
75
100
125
150
175
T
C
, Case Temperature ( ° C)
10%
V
GS
t
d(on)
t
r
t
d(off)
t
f
Fig 9.
Maximum Drain Current Vs.
Case Temperature
Fig 10b.
Switching Time Waveforms
1
Thermal Response (Z
thJC
)
D = 0.50
0.20
0.1
0.10
0.05
0.02
0.01
P
DM
t
1
SINGLE PULSE
(THERMAL RESPONSE)
Notes:
1. Duty factor D = t
1
/ t
2
2. Peak T
J
= P
DM
x Z
thJC
+ T
C
0.0001
0.001
0.01
0.1
1
t
2
0.01
0.00001
t
1
, Rectangular Pulse Duration (sec)
Fig 11.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
FPGA/CPLD
