IS41LV16257B-60TL,IS41LV16257B-60TL pdf中文资料,IS41LV16257B-60TL引脚图,IS41LV16257B-60TL电路-Datasheet-电子工程世界

文档预览

IS41LV16257B

256K x 16 (4-MBIT) DYNAMIC RAM

WITH FAST PAGE MODE

DESCRIPTION

The

ISSI

IS41LV16257B is 262,144 x 16-bit high-

performance CMOS Dynamic Random Access

Memories. Fast Page Mode allows 512 random

accesses within a single row with access cycle time as

short as 12 ns per 16-bit word. The Byte Write control,

of upper and lower byte, makes these devices ideal for

use in 16- and 32-bit wide data bus systems.

These features make the IS41LV16257B ideally suited

for high band-width graphics, digital signal processing,

high-performance computing systems, and peripheral

applications.

The IS41LV16257B is packaged in a 40-pin, 400-mil

SOJ and TSOP (Type II).

JUNE 2007

FEATURES

•

Fast access and cycle time

TTL compatible inputs and outputs

Refresh Interval: 512 cycles/8 ms

Refresh Mode:

RAS-Only, CAS-before-RAS

(CBR), and Hidden

JEDEC standard pinout

Single power supply: 3.3V ± 10%

Byte Write and Byte Read operation via

two

CAS

Lead-free available

KEY TIMING PARAMETERS

Parameter

Max.

RAS

Access Time (t

RAC

)

Max.

CAS

Access Time (t

CAC

)

Max. Column Address Access Time (t

)

Min. Fast Page Mode Cycle Time (t

)

Min. Read/Write Cycle Time (t

)

-35

-60

110

Unit

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc.

Rev. C

06/18/07

IS41LV16257B

FUNCTIONAL BLOCK DIAGRAM

LCAS

UCAS

CAS

CLOCK

GENERATOR

CONTROL

LOGICS

CONTROL

LOGIC

CAS

RAS

CLOCK

GENERATOR

DATA I/O BUS

REFRESH

COUNTER

DATA I/O BUFFERS

ROW DECODER

RAS

COLUMN DECODERS

SENSE AMPLIFIERS

I/O0-I/O15

MEMORY ARRAY

262,144 x 16

ADDRESS

BUFFERS

A0-A8

PIN CONFIGURATIONS

40-Pin TSOP (Type II)

VDD

I/O0

I/O1

I/O2

I/O3

VDD

I/O4

I/O5

I/O6

I/O7

GND

I/O15

I/O14

I/O13

I/O12

GND

I/O11

I/O10

I/O9

I/O8

PIN DESCRIPTIONS

40-Pin SOJ

VDD

I/O0

I/O1

I/O2

I/O3

VDD

I/O4

I/O5

I/O6

I/O7

GND

I/O15

I/O14

I/O13

I/O12

GND

I/O11

I/O10

I/O9

I/O8

LCAS

UCAS

GND

A0-A8

I/O0-I/O15

RAS

UCAS

LCAS

GND

Address Inputs

Data Inputs/Outputs

Write Enable

Output Enable

Row Address Strobe

Upper Column Address

Strobe

Lower Column Address

Strobe

Power

Ground

No Connection

RAS

VDD

LCAS

UCAS

GND

RAS

VDD

Integrated Silicon Solution, Inc.

Rev. C

06/18/07

IS41LV16257B

TRUTH TABLE

Function

Standby

Read: Word

Read: Lower Byte

Read: Upper Byte

Write: Word (Early Write)

Write: Lower Byte (Early Write)

Write: Upper Byte (Early Write)

Read-Write

(1,2)

Hidden Refresh

RAS-Only

Refresh

CBR Refresh

(3)

RAS

Read L∅H∅L

Write L∅H∅L

H∅L

LCAS

UCAS

H∅L

L∅H

Address t

ROW/COL

ROW/NA

I/O

High-Z

OUT

Lower Byte, D

OUT

Upper Byte, High-Z

Lower Byte, High-Z

Upper Byte, D

OUT

Lower Byte, D

Upper Byte, High-Z

Lower Byte, High-Z

Upper Byte, D

OUT

, D

OUT

High-Z

Notes:

1. These WRITE cycles may also be BYTE WRITE cycles (either

LCAS

UCAS

active).

2. These READ cycles may also be BYTE READ cycles (either

LCAS

UCAS

active).

3. At least one of the two CAS signals must be active (LCAS or

UCAS).

Integrated Silicon Solution, Inc.

Rev. C

06/18/07

IS41LV16257B

FUNCTIONAL DESCRIPTION

The IS41LV16257B is a CMOS DRAM optimized for high-

speed bandwidth, low-power applications. During READ or

WRITE cycles, each bit is uniquely addressed through the

18 address bits. These are entered nine bits (A0-A8) at a

time. The row address is latched by the Row Address Strobe

(RAS). The column address is latched by the Column

Address Strobe (CAS).

RAS

is used to latch the first nine bits

and

CAS

is used to latch the latter nine bits.

The IS41LV16257B has two

CAS

controls,

LCAS

and

UCAS.

The

LCAS

and

UCAS

inputs internally generate a

CAS

signal functioning in an identical manner to the single

CAS

input on the other 256K x 16 DRAMs. The key difference

is that each

CAS

controls its corresponding I/O tristate logic

(in conjunction with

and

RAS). LCAS

controls

I/O0 - I/O7 and

UCAS

controls I/O8 - I/O15.

The IS41LV16257B

CAS

function is determined by the first

CAS

(LCAS or

UCAS)

transitioning LOW and the last

transitioning back HIGH. The two

CAS

controls give the

IS41LV16257B both BYTE READ and BYTE WRITE cycle

capabilities.

Write Cycle

A write cycle is initiated by the falling edge of

CAS

and

WE,

whichever occurs last. The input data must be valid at or

before the falling edge of

CAS

WE,

whichever occurs last.

Refresh Cycle

To retain data, 512 refresh cycles are required in each

8 ms period. There are two ways to refresh the memory:

1. By clocking each of the 512 row addresses (A0 through

A8) with

RAS

at least once every 8 ms. Any read, write,

read-modify-write or

RAS-only

cycle refreshes the ad-

dressed row.

2. Using a

CAS-before-RAS

refresh cycle.

CAS-before-

RAS

refresh is activated by the falling edge of

RAS,

while

holding

CAS

LOW. In

CAS-before-RAS

refresh cycle, an

internal 9-bit counter provides the row addresses and the

external address inputs are ignored.

CAS-before-RAS

is a refresh-only mode and no data access

or device selection is allowed. Thus, the output remains in

the High-Z state during the cycle.

Memory Cycle

A memory cycle is initiated by bringing

RAS

LOW and it is

terminated by returning both

RAS

and

CAS

HIGH. To

ensure proper device operation and data integrity any

memory cycle, once initiated, must not be ended or aborted

before the minimum t

RAS

time has expired. A new cycle

must not be initiated until the minimum precharge time t

has elapsed.

Power-On

After application of the V

supply, an initial pause of

200 µs is required followed by a minimum of eight initialization

cycles (any combination of cycles containing a

RAS

signal).

During power-on, it is recommended that

RAS

track with V

or be held at a valid V

to avoid current surges.

Read Cycle

A read cycle is initiated by the falling edge of

CAS

OE,

whichever occurs last, while holding

HIGH. The column

address must be held for a minimum time specified by t

Data Out becomes valid only when t

RAC

, t

CAC

and t

OEA

are all satisfied. As a result, the access time is dependent

on the timing relationships between these parameters.

Integrated Silicon Solution, Inc.

Rev. C

06/18/07

IS41LV16257B

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

OUT

STG

Parameters

Voltage on Any Pin Relative to GND

Supply Voltage

Output Current

Power Dissipation

Operation Temperature

Storage Temperature

3.3V

Rating

–0.5 t0 +4.6

0 to +70

-40 to +85

–55 to +125

Unit

°C

Com.

Ind.

Note:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-

nent damage to the device. This is a stress rating only and functional operation of the device

at these or any other conditions above those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for extended

periods may affect reliability.

RECOMMENDED OPERATING CONDITIONS

(Voltages are referenced to GND)

Symbol

Parameter

Supply Voltage

Input High Voltage

Input Low Voltage

Ambient Temperature

Voltage

3.3V

3.3

Com.

Ind.

Min.

3.0

2.0

–0.3

-40

Typ.

3.3

—

Max.

3.6

+ 0.3

0.8

Unit

°C

CAPACITANCE

(1,2)

Symbol

Parameter

Input Capacitance: A0-A8

Input Capacitance:

RAS, UCAS, LCAS, WE, OE

Data Input/Output Capacitance: I/O0-I/O15

Max.

Unit

Notes:

1. Tested initially and after any design or process changes that may affect these parameters.

2. Test conditions: T

= 25°C, f = 1 MHz, V

=3.3V ± 10%.

Integrated Silicon Solution, Inc.

Rev. C

06/18/07

参数对比

与IS41LV16257B-60TL相近的元器件有：IS41LV16257B-35TL、IS41LV16257B-35KLI、IS41LV16257B-35TL-TR、IS41LV16257B-60KL、IS41LV16257B-60K、IS41LV16257B-60T。描述及对比如下：

型号	IS41LV16257B-60TL	IS41LV16257B-35TL	IS41LV16257B-35KLI	IS41LV16257B-35TL-TR	IS41LV16257B-60KL	IS41LV16257B-60K	IS41LV16257B-60T
描述	Fast Page DRAM, 256KX16, 60ns, CMOS, PDSO40, 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-40	Fast Page DRAM, 256KX16, 35ns, CMOS, PDSO40, 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-40	Fast Page DRAM, 256KX16, 35ns, CMOS, PDSO40, 0.400 INCH, LEAD FREE, PLASTIC, SOJ-40	Fast Page DRAM, 256KX16, 35ns, CMOS, PDSO40, 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-40	Fast Page DRAM, 256KX16, 60ns, CMOS, PDSO40, 0.400 INCH, LEAD FREE, PLASTIC, SOJ-40	Fast Page DRAM, 256KX16, 60ns, CMOS, PDSO40, 0.400 INCH, PLASTIC, SOJ-40	Fast Page DRAM, 256KX16, 60ns, CMOS, PDSO40, 0.400 INCH, PLASTIC, TSOP2-40
是否Rohs认证	符合	符合	符合	符合	符合	不符合	不符合
厂商名称	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )
零件包装代码	TSOP2	TSOP2	SOJ	TSOP2	SOJ	SOJ	TSOP2
包装说明	TSOP2, TSOP40/44,.46,32	TSOP2, TSOP40/44,.46,32	SOJ,	TSOP2,	SOJ, SOJ40,.44	0.400 INCH, PLASTIC, SOJ-40	0.400 INCH, PLASTIC, TSOP2-40
针数	40	40	40	40	40	40	40
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	unknown	unknown
ECCN代码	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
访问模式	FAST PAGE	FAST PAGE	FAST PAGE	FAST PAGE	FAST PAGE	FAST PAGE	FAST PAGE
最长访问时间	60 ns	35 ns	35 ns	35 ns	60 ns	60 ns	60 ns
其他特性	RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH	RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH	RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH	RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH	RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH	RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH	RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH
JESD-30 代码	R-PDSO-G40	R-PDSO-G40	R-PDSO-J40	R-PDSO-G40	R-PDSO-J40	R-PDSO-J40	R-PDSO-G40
JESD-609代码	e3	e3	e3	e3	e3	e0	e0
长度	18.41 mm	18.41 mm	26.035 mm	18.41 mm	26.035 mm	26.035 mm	18.41 mm
内存密度	4194304 bit	4194304 bit	4194304 bit	4194304 bit	4194304 bit	4194304 bit	4194304 bit
内存集成电路类型	FAST PAGE DRAM	FAST PAGE DRAM	FAST PAGE DRAM	FAST PAGE DRAM	FAST PAGE DRAM	FAST PAGE DRAM	FAST PAGE DRAM
内存宽度	16	16	16	16	16	16	16
湿度敏感等级	3	3	3	3	3	3	3
功能数量	1	1	1	1	1	1	1
端口数量	1	1	1	1	1	1	1
端子数量	40	40	40	40	40	40	40
字数	262144 words	262144 words	262144 words	262144 words	262144 words	262144 words	262144 words
字数代码	256000	256000	256000	256000	256000	256000	256000
工作模式	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
最高工作温度	70 °C	70 °C	85 °C	70 °C	70 °C	70 °C	70 °C
组织	256KX16	256KX16	256KX16	256KX16	256KX16	256KX16	256KX16
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	TSOP2	TSOP2	SOJ	TSOP2	SOJ	SOJ	TSOP2
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE
峰值回流温度（摄氏度）	260	260	260	260	260	NOT SPECIFIED	NOT SPECIFIED
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	1.2 mm	1.2 mm	3.75 mm	1.2 mm	3.75 mm	3.75 mm	1.2 mm
最大供电电压 (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
最小供电电压 (Vsup)	3 V	3 V	3 V	3 V	3 V	3 V	3 V
标称供电电压 (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
表面贴装	YES	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
端子面层	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed	MATTE TIN	Matte Tin (Sn) - annealed	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
端子形式	GULL WING	GULL WING	J BEND	GULL WING	J BEND	J BEND	GULL WING
端子节距	0.8 mm	0.8 mm	1.27 mm	0.8 mm	1.27 mm	1.27 mm	0.8 mm
端子位置	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
处于峰值回流温度下的最长时间	40	40	40	40	40	NOT SPECIFIED	NOT SPECIFIED
宽度	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm
I/O 类型	COMMON	COMMON	-	-	COMMON	COMMON	COMMON
输出特性	3-STATE	3-STATE	-	-	3-STATE	3-STATE	3-STATE
封装等效代码	TSOP40/44,.46,32	TSOP40/44,.46,32	-	-	SOJ40,.44	SOJ40,.44	TSOP40/44,.46,32
电源	3.3 V	3.3 V	-	-	3.3 V	3.3 V	3.3 V
刷新周期	512	512	-	-	512	512	512
自我刷新	NO	NO	-	-	NO	NO	NO
最大待机电流	0.001 A	0.001 A	-	-	0.001 A	0.001 A	0.001 A
最大压摆率	0.17 mA	0.23 mA	-	-	0.17 mA	0.17 mA	0.17 mA