IS41C85125
IS41LV85125
512K x 8 (4-MBIT) DYNAMIC RAM
WITH FAST PAGE MODE
FEATURES
Fast access and cycle time
TTL compatible inputs and outputs
Refresh Interval: 1024 cycles/16 ms
Refresh Mode:
RAS-Only, CAS-before-RAS
(CBR), and Hidden
• JEDEC standard pinout
• Single power supply:
-- 5V ± 10% (IS41C85125)
-- 3.3V ± 10% (IS41LV85125)
• Industrial temperature available
•
•
•
•
ISSI
DESCRIPTION
®
PRELIMINARY INFORMATION
AUGUST 2001
The
ISSI
IS41C85125 and IS41LV85125 are 512,288 x 8-bit
high-performance CMOS Dynamic Random Access
Memories. Fast Page Mode allows 1024 random accesses
within a single row with access cycle time as short as 12
ns per 8-bit word.
These features make the IS41C85125 and the IS41LV85125
ideally suited for high band-width graphics, digital signal
processing, high-performance computing systems, and
peripheral applications.
The IS41C85125 and IS41LV85125 are available in a
28-pin, 400-mil SOJ package.
KEY TIMING PARAMETERS
Parameter
Max.
RAS
Access Time (t
RAC
)
Max.
CAS
Access Time (t
CAC
)
Max. Column Address Access Time (t
AA
)
Min. Fast Page Mode Cycle Time (t
PC
)
Min. Read/Write Cycle Time (t
RC
)
-35
35
10
18
12
60
-60
60
15
30
25
110
Unit
ns
ns
ns
ns
ns
PIN CONFIGURATION
28-Pin SOJ
V
CC
I/O0
I/O1
I/O2
I/O3
NC
WE
RAS
A9
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
I/O7
I/O6
I/O5
I/O4
CAS
OE
NC
A8
A7
A6
A5
A4
GND
PIN DESCRIPTIONS
A0-A9
I/O0-I/O7
WE
OE
RAS
CAS
V
CC
GND
NC
Address Inputs
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Column Address Strobe
Power
Ground
No Connection
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the
best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
09/25/01
Rev. 00A
1
IS41C85125
IS41LV85125
FUNCTIONAL BLOCK DIAGRAM
ISSI
®
OE
WE
CAS
CAS
CLOCK
GENERATOR
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
OE
RAS
CAS
WE
RAS
RAS
CLOCK
GENERATOR
DATA I/O BUS
COLUMN DECODERS
SENSE AMPLIFIERS
REFRESH
COUNTER
DATA I/O BUFFERS
I/O0-I/O7
ROW DECODER
ADDRESS
BUFFERS
A0-A9
MEMORY ARRAY
512,288 x 8
TRUTH TABLE
Function
Standby
Read
Write: Word (Early Write)
Read-Write
Hidden Refresh
Read
Write
(1)
RAS-Only
Refresh
CBR Refresh
Notes:
1. EARLY WRITE only.
RAS
H
L
L
L
L→H→L
L→H→L
L
H→L
CAS
H
L
L
L
L
L
H
L
WE
X
H
L
H→L
H
L
X
X
OE
X
L
X
L→H
L
X
X
X
Address t
R
/t
C
X
ROW/COL
ROW/COL
ROW/COL
ROW/COL
ROW/COL
ROW/NA
X
I/O
High-Z
D
OUT
D
IN
D
OUT
, D
IN
D
OUT
D
OUT
High-Z
High-Z
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
09/25/01
IS41C85125
IS41LV85125
FUNCTIONAL DESCRIPTION
The IS41C85125 and IS41LV85125 are CMOS DRAMs
optimized for high-speed bandwidth, low-power
applications. During READ or WRITE cycles, each bit is
uniquely addressed through the 19 address bits. The first
ten address bits (A0-A9) are entered as row address and
latter nine address bits (A0-A8) are entered as column
address. The row address is latched by the Row Address
Strobe (RAS). The column address is latched by the
Column Address Strobe (CAS).
RAS
is used to latch the
first ten bits of row address and
CAS
is used to latch the
latter nine bits of column address.
ISSI
Refresh Cycle
®
at or before the falling edge of
CAS
or
WE,
whichever
occurs last.
To retain data, 1024 refresh cycles are required in each
16 ms period. There are two ways to refresh the memory:
1. By clocking each of the 1024 row addresses (A0
through A9) with
RAS
at least once every 16 ms. Any
read, write, read-modify-write or
RAS-only
cycle re-
freshes the addressed row.
2. Using a
CAS-before-RAS
refresh cycle.
CAS-before-
RAS
refresh is activated by the falling edge of
RAS,
while holding
CAS
LOW. In
CAS-before-RAS
refresh
cycle, an internal 10-bit counter provides the row
addresses and the external address inputs are ignored.
CAS-before-RAS
is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Memory Cycle
A memory cycle is initiated by bringing
RAS
LOW and it
is terminated by returning both
RAS
and
CAS
HIGH. To
ensure proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum t
RAS
time has expired. A new
cycle must not be initiated until the minimum precharge
time t
RP
, t
CP
has elapsed.
Power-On
After application of the V
CC
supply, an initial pause of
200 µs is required followed by a minimum of eight
initialization cycles (any combination of cycles containing
a
RAS
signal).
During power-on, it is recommended that
RAS
track with
V
CC
or be held at a valid V
IH
to avoid current surges.
Read Cycle
A read cycle is initiated by the falling edge of
CAS
or
OE,
whichever occurs last, while holding
WE
HIGH. The
column address must be held for a minimum time specified
by t
AR
. Data Out becomes valid only when t
RAC
, t
AA
, t
CAC
and t
OEA
are all satisfied. As a result, the access time is
dependent on the timing relationships between these
parameters.
Write Cycle
A write cycle is initiated by the falling edge of
CAS
and
WE,
whichever occurs last. The input data must be valid
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
09/25/01
Rev. 00A
3
IS41C85125
IS41LV85125
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
T
V
CC
I
OUT
P
D
T
A
T
STG
Parameters
Voltage on Any Pin Relative to GND
Supply Voltage
Output Current
Power Dissipation
Operation Temperature
Storage Temperature
5V
3.3V
5V
3.3V
Rating
–1.0 to +7.0
–0.5 t0 +4.6
–1.0 to +7.0
–0.5 t0 +4.6
50
1
0 to 70
–40 to +85
–55 to +125
Unit
V
V
mA
W
°C
°C
ISSI
®
Com.
Ind.
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltages are referenced to GND)
Symbol
V
CC
V
CC
V
IH
V
IH
V
IL
V
IL
T
A
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input High Voltage
Input Low Voltage
Input Low Voltage
Ambient Temperature
Voltage
5V
3.3V
5V
3.3V
5V
3.3
Com.
Ind.
Min.
4.5
3.0
2.4
2.0
–1.0
–0.3
0
–40
Typ.
5.0
3.3
—
—
—
—
—
—
Max.
5.5
3.6
V
CC
+ 1.0
V
CC
+ 0.3
0.8
0.8
70
85
Unit
V
V
V
V
V
V
°C
CAPACITANCE
(1,2)
Symbol
C
IN
1
C
IN
2
C
IO
Parameter
Input Capacitance: A0-A9
Input Capacitance:
RAS, UCAS, LCAS, WE, OE
Data Input/Output Capacitance: I/O0-I/O7
Max.
5
7
7
Unit
pF
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25°C, f = 1 MHz.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
09/25/01
IS41C85125
IS41LV85125
ELECTRICAL CHARACTERISTICS
(1)
(Recommended Operation Conditions unless otherwise noted.)
Symbol
I
IL
I
IO
V
OH
V
OL
I
CC1
Parameter
Input Leakage Current
Output Leakage Current
Output High Voltage Level
Output Low Voltage Level
Stand-by Current: TTL
Test Condition
Any input 0V
≤
V
IN
≤
Vcc
Other inputs not under test = 0V
Output is disabled (Hi-Z)
0V
≤
V
OUT
≤
Vcc
I
OH
= –2.5 mA
I
OL
= 2.1 mA
RAS, CAS
≥
V
IH
5V
5V
3.3V
3.3V
5V
3.3V
Com.
Ind.
Com.
Ind.
Speed
Min.
–10
–10
2.4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ISSI
Max.
10
10
—
0.4
2
3
1
2
2
1
230
170
220
160
230
170
230
170
µA
µA
V
V
mA
®
Unit
I
CC2
I
CC3
Stand-by Current: CMOS
Operating Current:
Random Read/Write
(2,3,4)
Average Power Supply Current
Operating Current:
Fast Page Mode
(2,3,4)
Average Power Supply Current
Refresh Current:
RAS-Only
(2,3)
Average Power Supply Current
Refresh Current:
CBR
(2,3,5)
Average Power Supply Current
RAS, CAS
≥
V
CC
– 0.2V
mA
mA
RAS, CAS,
Address Cycling, t
RC
= t
RC
(min.)
RAS
= V
IL
,
CAS,
Cycling t
PC
= t
PC
(min.)
RAS
Cycling,
CAS
≥
V
IH
t
RC
= t
RC
(min.)
RAS, CAS
Cycling
t
RC
= t
RC
(min.)
-35
-60
-35
-60
-35
-60
-35
-60
I
CC4
mA
I
CC5
mA
I
CC6
mA
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight
RAS
refresh cycles (RAS-Only or CBR) before proper device
operation is assured.The eight
RAS
cycles wake-up should be repeated any time the t
REF
refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each fast page cycle.
5. Enables on-chip refresh and address counters.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
09/25/01
Rev. 00A
5
