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IS42VS16100D

512K Words x 16 Bits x 2 Banks (16-MBIT)

SYNCHRONOUS DYNAMIC RAM

ISSI

DESCRIPTION

ISSI

’s 16Mb Synchronous DRAM IS42VS16100D is

organized as a 524,288-word x 16-bit x 2-bank for

improved performance. The synchronous DRAMs

achieve high-speed data transfer using pipeline

architecture. All inputs and outputs signals refer to the

rising edge of the clock input.

ADVANCED INFORMATION

JULY 2005

FEATURES

• Clock frequency: 135, 100, 83 MHz

•

Power Supply: 1.8V

•

Fully synchronous; all signals referenced to a

positive clock edge

•

Two banks can be operated simultaneously and

independently

•

Dual internal bank controlled by A11 (bank

select)

•

Programmable burst length (1, 2, 4, 8, full page)

•

Programmable burst sequence: Sequential/

Interleave

•

Programmable full and half drive strength

•

Programmable

CAS

latency (2, 3 clocks)

•

2048 refresh cycles every 32 ms

•

Random column address every clock cycle

•

Burst read/write and burst read/single write

operations capability

•

Byte controlled by LDQM and UDQM

•

Auto Refresh and Self Refresh modes

•

Partial Array Self-Refresh

•

Power Down and Deep Power Down

•

Lead-free package options

KEY TIMING PARAMETERS

Parameter

Clock Cycle Time

CAS

Latency = 3

CAS

Latency = 2

Clock Frequency

CAS

Latency = 3

CAS

Latency = 2

Access Time from Clock

CAS

Latency = 3

CAS

Latency = 2

-7.5

7.4

133

100

-10

100

Unit

MHz

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — www.issi.com —

1-800-379-4774

Rev. 00D

06/30/05

IS42VS16100D

ISSI

GND

DQ15

IDQ14

GNDQ

DQ13

DQ12

VDDQ

DQ11

DQ10

GNDQ

DQ9

DQ8

VDDQ

UDQM

CLK

CKE

GND

PIN CONFIGURATIONS

50-Pin TSOP (Type II)

VDD

DQ0

DQ1

GNDQ

DQ2

DQ3

VDDQ

DQ4

DQ5

GNDQ

DQ6

DQ7

VDDQ

LDQM

CAS

RAS

A11

A10

VDD

PIN DESCRIPTIONS

A0-A11

A0-A10

A11

A0-A7

DQ0 to DQ15

CLK

CKE

RAS

Address Input

Row Address Input

Bank Select Address

Column Address Input

Data DQ

System Clock Input

Clock Enable

Chip Select

Row Address Strobe Command

CAS

LDQM

UDQM

VDD

GND

VDDQ

GNDQ

Column Address Strobe Command

Write Enable

Lower Bye, Input/Output Mask

Upper Bye, Input/Output Mask

Power

Ground

Power Supply for DQ Pin

Ground for DQ Pin

No Connection

Integrated Silicon Solution, Inc. — www.issi.com —

1-800-379-4774

Rev. 00D

06/30/05

IS42VS16100D

PIN FUNCTIONS

Pin No.

20 to 24

27 to 32

Symbol

A0-A10

Type

Input Pin

Function (In Detail)

ISSI

A0 to A10 are address inputs. A0-A10 are used as row address inputs during active

command input and A0-A7 as column address inputs during read or write command

input. A10 is also used to determine the precharge mode during other commands. If

A10 is LOW during precharge command, the bank selected by A11 is precharged,

but if A10 is HIGH, both banks will be precharged.

When A10 is HIGH in read or write command cycle, the precharge starts

automatically after the burst access.

These signals become part of the OP CODE during mode register set command

input.

A11 is the bank selection signal. When A11 is LOW, bank 0 is selected and when

high, bank 1 is selected. This signal becomes part of the OP CODE during mode

CAS,

in conjunction with the

RAS

and

WE,

forms the device command. See the

“Command Truth Table” item for details on device commands.

The CKE input determines whether the CLK input is enabled within the device. When

is CKE HIGH, the next rising edge of the CLK signal will be valid, and when LOW,

invalid. When CKE is LOW, the device will be in either the power-down mode, the

clock suspend mode, or the self refresh mode. The CKE is an asynchronous input.

CLK is the master clock input for this device. Except for CKE, all inputs to this device

are acquired in synchronization with the rising edge of this pin.

The

input determines whether command input is enabled within the device.

Command input is enabled when

is LOW, and disabled with

is HIGH. The

device remains in the previous state when

is HIGH.

DQ0 to DQ15 are DQ pins. DQ through these pins can be controlled in byte units

using the LDQM and UDQM pins.

LDQM and UDQM control the lower and upper bytes of the DQ buffers. In read

mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW,

the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go

to the HIGH impedance state when LDQM/UDQM is HIGH. This function

corresponds to

in conventional DRAMs. In write mode, LDQM and UDQM control

the input buffer. When LDQM or UDQM is LOW, the corresponding buffer byte is

enabled, and data can be written to the device. When LDQM or UDQM is HIGH, input

data is masked and cannot be written to the device.

RAS,

in conjunction with

CAS

and

WE,

forms the device command. See the

“Command Truth Table” item for details on device commands.

WE,

in conjunction with

RAS

and

CAS,

forms the device command. See the

“Command Truth Table” item for details on device commands.

VDDQ is the output buffer power supply.

VDD is the device internal power supply.

GNDQ is the output buffer ground.

GND is the device internal ground.

A11

Input Pin

CAS

CKE

Input Pin

CLK

Input Pin

2, 3, 5, 6, 8, 9, 11

12, 39, 40, 42, 43,

45, 46, 48, 49

14, 36

DQ0 to

DQ15

LDQM,

UDQM

DQ Pin

Input Pin

7, 13, 38, 44

1, 25

4, 10, 41, 47

26, 50

RAS

VDDQ

VDD

GNDQ

GND

Input Pin

Power Supply Pin

Integrated Silicon Solution, Inc. — www.issi.com —

1-800-379-4774

Rev. 00D

06/30/05

IS42VS16100D

FUNCTIONAL BLOCK DIAGRAM

ISSI

COMMAND

DECODER

CLOCK

GENERATOR

ROW DECODER

CLK

CKE

RAS

CAS

A11

MODE

ROW

ADDRESS

BUFFER

MEMORY CELL

ARRAY

2048

BANK 0

LDQM

UDQM

SENSE AMP I/O GATE

A10

COLUMN

ADDRESS BUFFER

BURST COUNTER

COLUMN

ADDRESS LATCH

DATA IN

BUFFER

256

COLUMN DECODER

ROW DECODER

MULTIPLEXER

REFRESH

CONTROLLER

SELF

REFRESH

CONTROLLER

DQ 0-15

256

SENSE AMP I/O GATE

REFRESH

COUNTER

DATA OUT

BUFFER

ROW

ADDRESS

LATCH

ROW

ADDRESS

BUFFER

2048

MEMORY CELL

ARRAY

VDD/VDDQ

GND/GNDQ

BANK 1

Integrated Silicon Solution, Inc. — www.issi.com —

1-800-379-4774

Rev. 00D

06/30/05

IS42VS16100D

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

MAX

DDQ

MAX

D MAX

OPR

STG

Parameters

Maximum Supply Voltage

Maximum Supply Voltage for Output Buffer

Input Voltage

Allowable Power Dissipation

Output Shorted Current

Operating Temperature

Storage Temperature

Com

Ext.

Rating

–0.5 to +2.6

0 to +70

-25 to +85

–55 to +150

Unit

°C

ISSI

DC RECOMMENDED OPERATING CONDITIONS

(2)

Commercial

(

= 0°C to +70°C), Extended

(

= -25°C to +85°C)

Symbol

, V

DDQ

Parameter

Supply Voltage

Input High Voltage

(3)

Input Low Voltage

(4)

Min.

1.7

0.8 x V

DDQ

-0.3

Typ.

1.8

—

Max.

1.9

DDQ

+ 0.3

+0.3

Unit

CAPACITANCE CHARACTERISTICS

(1,2)

= 1.8V, T

= +25°C, f = 1 MHz)

Symbol

CI/O

Parameter

Input Capacitance: CLK

Input Capacitance: (A0-A11, CKE,

CS, RAS, CAS, WE,

LDQM, UDQM)

Data Input/Output Capacitance: DQ0-DQ15

Min.

2.5

4.0

Max.

4.0

5.0

6.5

Unit

Notes:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This

is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the

operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended

periods may affect reliability.

2. All voltages are referenced to Vss.

3. V

(max) = 2.2V with a pulse width

≤

3 ns.

4. V

(min) = -1.0V with a pulse width

≤

3 ns.

Integrated Silicon Solution, Inc. — www.issi.com —

1-800-379-4774

Rev. 00D

06/30/05

参数对比

与IS42VS16100D-75TL相近的元器件有：IS42VS16100D-10TL、IS42VS16100D-10TLE、IS42VS16100D-75T、IS42VS16100D-75TLE、IS42VS16100D-75TE、IS42VS16100D-10T、IS42VS16100D-10TE。描述及对比如下：

型号	IS42VS16100D-75TL	IS42VS16100D-10TL	IS42VS16100D-10TLE	IS42VS16100D-75T	IS42VS16100D-75TLE	IS42VS16100D-75TE	IS42VS16100D-10T	IS42VS16100D-10TE
描述	Synchronous DRAM, 1MX16, 6ns, CMOS, PDSO50, LEAD FREE, PLASTIC, TSOP2-50	Synchronous DRAM, 1MX16, 7ns, CMOS, PDSO50, LEAD FREE, PLASTIC, TSOP2-50	Synchronous DRAM, 1MX16, 7ns, CMOS, PDSO50, LEAD FREE, PLASTIC, TSOP2-50	Synchronous DRAM, 1MX16, 6ns, CMOS, PDSO50, PLASTIC, TSOP2-50	Synchronous DRAM, 1MX16, 6ns, CMOS, PDSO50, LEAD FREE, PLASTIC, TSOP2-50	Synchronous DRAM, 1MX16, 6ns, CMOS, PDSO50, PLASTIC, TSOP2-50	Synchronous DRAM, 1MX16, 7ns, CMOS, PDSO50, PLASTIC, TSOP2-50	Synchronous DRAM, 1MX16, 7ns, CMOS, PDSO50, PLASTIC, TSOP2-50
是否无铅	不含铅	不含铅	不含铅	含铅	不含铅	含铅	含铅	含铅
是否Rohs认证	符合	符合	符合	不符合	符合	不符合	不符合	不符合
零件包装代码	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2
包装说明	TSOP2, TSOP50,.46,32	TSOP2, TSOP50,.46,32	TSOP2, TSOP50,.46,32	TSOP2, TSOP50,.46,32	TSOP2, TSOP50,.46,32	TSOP2, TSOP50,.46,32	TSOP2, TSOP50,.46,32	TSOP2, TSOP50,.46,32
针数	50	50	50	50	50	50	50	50
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant
ECCN代码	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
访问模式	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST
最长访问时间	6 ns	7 ns	7 ns	6 ns	6 ns	6 ns	7 ns	7 ns
其他特性	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	133 MHz	100 MHz	100 MHz	133 MHz	133 MHz	133 MHz	100 MHz	100 MHz
I/O 类型	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
交错的突发长度	1,2,4,8	1,2,4,8	1,2,4,8	1,2,4,8	1,2,4,8	1,2,4,8	1,2,4,8	1,2,4,8
JESD-30 代码	R-PDSO-G50	R-PDSO-G50	R-PDSO-G50	R-PDSO-G50	R-PDSO-G50	R-PDSO-G50	R-PDSO-G50	R-PDSO-G50
JESD-609代码	e3	e3	e3	e0	e3	e0	e0	e0
长度	20.95 mm	20.95 mm	20.95 mm	20.95 mm	20.95 mm	20.95 mm	20.95 mm	20.95 mm
内存密度	16777216 bit	16777216 bit	16777216 bit	16777216 bit	16777216 bit	16777216 bit	16777216 bit	16777216 bit
内存集成电路类型	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM
内存宽度	16	16	16	16	16	16	16	16
湿度敏感等级	3	3	3	3	3	3	3	3
功能数量	1	1	1	1	1	1	1	1
端口数量	1	1	1	1	1	1	1	1
端子数量	50	50	50	50	50	50	50	50
字数	1048576 words	1048576 words	1048576 words	1048576 words	1048576 words	1048576 words	1048576 words	1048576 words
字数代码	1000000	1000000	1000000	1000000	1000000	1000000	1000000	1000000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	70 °C	70 °C	85 °C	70 °C	85 °C	85 °C	70 °C	85 °C
组织	1MX16	1MX16	1MX16	1MX16	1MX16	1MX16	1MX16	1MX16
输出特性	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2
封装等效代码	TSOP50,.46,32	TSOP50,.46,32	TSOP50,.46,32	TSOP50,.46,32	TSOP50,.46,32	TSOP50,.46,32	TSOP50,.46,32	TSOP50,.46,32
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE
峰值回流温度（摄氏度）	260	260	260	NOT SPECIFIED	260	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
电源	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
刷新周期	2048	2048	2048	2048	2048	2048	2048	2048
座面最大高度	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm
自我刷新	YES	YES	YES	YES	YES	YES	YES	YES
连续突发长度	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP
最大待机电流	0.00001 A	0.00001 A	0.00001 A	0.00001 A	0.00001 A	0.00001 A	0.00001 A	0.00001 A
最大压摆率	0.06 mA	0.05 mA	0.05 mA	0.06 mA	0.06 mA	0.06 mA	0.05 mA	0.05 mA
最大供电电压 (Vsup)	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V
最小供电电压 (Vsup)	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V
标称供电电压 (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
表面贴装	YES	YES	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	COMMERCIAL	OTHER	COMMERCIAL	OTHER	OTHER	COMMERCIAL	OTHER
端子面层	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed	Tin/Lead (Sn/Pb)	Matte Tin (Sn) - annealed	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
端子形式	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
端子节距	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm
端子位置	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
处于峰值回流温度下的最长时间	40	40	40	NOT SPECIFIED	40	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
宽度	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm
厂商名称	Integrated Silicon Solution ( ISSI )	-	-	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )