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IS43R32800-75BL

Synchronous DRAM, 8MX32, 0.75ns, CMOS, PBGA144, 12 X 12 MM, 0.80 MM PITCH, LEAD FREE, FBGA-144

器件类别:存储    存储   

厂商名称:Integrated Silicon Solution ( ISSI )

器件标准:  

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器件参数
参数名称
属性值
是否无铅
不含铅
是否Rohs认证
符合
零件包装代码
BGA
包装说明
LFBGA, BGA144,12X12,32
针数
144
Reach Compliance Code
compliant
ECCN代码
EAR99
访问模式
FOUR BANK PAGE BURST
最长访问时间
0.75 ns
其他特性
AUTO/SELF REFRESH
最大时钟频率 (fCLK)
133 MHz
I/O 类型
COMMON
交错的突发长度
2,4,8
JESD-30 代码
S-PBGA-B144
JESD-609代码
e1
长度
12 mm
内存密度
268435456 bit
内存集成电路类型
SYNCHRONOUS DRAM
内存宽度
32
湿度敏感等级
3
功能数量
1
端口数量
1
端子数量
144
字数
8388608 words
字数代码
8000000
工作模式
SYNCHRONOUS
最高工作温度
70 °C
最低工作温度
组织
8MX32
输出特性
3-STATE
封装主体材料
PLASTIC/EPOXY
封装代码
LFBGA
封装等效代码
BGA144,12X12,32
封装形状
SQUARE
封装形式
GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度)
260
电源
2.5 V
认证状态
Not Qualified
刷新周期
4096
座面最大高度
1.4 mm
自我刷新
YES
连续突发长度
2,4,8
最大待机电流
0.035 A
最大压摆率
0.36 mA
最大供电电压 (Vsup)
2.7 V
最小供电电压 (Vsup)
2.3 V
标称供电电压 (Vsup)
2.5 V
表面贴装
YES
技术
CMOS
温度等级
COMMERCIAL
端子面层
Tin/Silver/Copper (Sn/Ag/Cu)
端子形式
BALL
端子节距
0.8 mm
端子位置
BOTTOM
处于峰值回流温度下的最长时间
40
宽度
12 mm
Base Number Matches
1
文档预览
IS43R32800
8Mx32
256Mb DDR Synchronous DRAM
FEATURES
V
dd
/V
ddq
=2.5V+0.2V (-5, -6, -75)
Double data rate architecture; two data transfers
per clock cycle
Bidirectional, data strobe (DQS) is transmitted/
received with data
Differential clock input (CLK and /CLK)
DLL aligns DQ and DQS transitions with CLK
transitions edges of DQS
Commands entered on each positive CLK edge;
Data and data mask referenced to both edges of
DQS
4 bank operation controlled by BA0, BA1 (Bank
Address)
/CAS latency –2.0/2.5/3.0 (programmable)
Burst length - 2/4/8 (programmable)
Burst type - Sequential/ Interleave (program-
mable)
Auto precharge / All bank precharge controlled
by A8
4096 refresh cycles/ 64ms (4 banks concurrent
refresh)
Auto refresh and Self refresh
Row address A0-11/ Column address A0-7, A9-
SSTL_2 Interface
Package 144-ball FBGA
Available in Industrial Temperature
Temperature Range:
Commercial (0
o
C to +70
o
C)
FEBUARY 2009
DESCRIPTION:
IS43R32800 is a 4-bank x 2,097,152-word x32bit
Double Data Rate Synchronous DRAM, with SSTL_2
interface. All control and address signals are referenced
to the rising edge of CLK. Input data is registered on
both edges of data strobe, and output data and data
strobe are referenced on both edges of CLK. The
IS43R32800 achieves very high speed clock rate up to
200 MHz . It is packaged in 144-ball FBGA.
KEY TIMING PARAMETERS
Parameter
-5
-6
-75
Clk Cycle Time
CAS Latency = 3
5
6
7.5
CAS Latency = 2.5
5
6
7.5
CAS Latency = 2
7.5
7.5
7.5
Clk Frequency
CAS Latency = 3
200
167
143
CAS Latency = 2.5 200
167
143
CAS Latency = 2
143
143
143
Access Time from Clock
CAS Latency = 3
+0.70 +0.70 +0.70
CAS Latency = 2.5 +0.70 +0.70 +0.70
CAS Latency = 2
+0.75 +0.75 +0.70
Unit
ns
ns
ns
MHz
MHz
MHz
ns
ns
ns
ADDRESS TABLE
Parameter
Configuration
Bank Address Pins
Autoprecharge Pins
Row Addresses
Column Addresses
Refresh Count
8M x 32
2M x 32 x 4 banks
BA0, BA1
A8/AP
A0 – A11
A0 – A7, A9
4096 / 64ms
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
01/14/09
1
IS43R32800
FUNCTIONAL BLOCK DIAGRAM
DQ 0 - 31
DQS0 - 3
DLL
I/O Buffer
DQ S B uffer
Memory
Array
Ba nk #0
Memory
Array
Ba nk #1
Memory
Array
Ba nk #2
Memory
Array
Ba nk #3
Mode Re gister
Control C ircu itry
Addres s B uffer
Cl ock B uffer
A0-1 1
BA 0,1
CLK
/CLK
CKE
Control Signal B uffer
/CS /RAS /CAS
/WE
D M0- 3
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev.
A
01/14/09
IS43R32800
PIN CONFIGURATION
Package Code: B 144-ball FBGA (Top View) (12.00mm x 12.00mm Body, 0.8mm Ball Pitch
1
A
B
C
D
E
F
G
H
J
K
L
M
DQS0
DQ 4
DQ 6
DQ 7
DQ 17
DQ 19
DQS2
DQ 21
DQ 22
/CAS
/R AS
/CS
2
DM0
VDDQ
DQ 5
VDDQ
DQ 16
DQ 18
DM2
DQ 20
DQ 23
/W E
NC
NC
3
VSSQ
NC
VSSQ
VD D
VDDQ
VDDQ
NC
VDDQ
VDDQ
VD D
NC
BA 0
4
DQ 3
VDDQ
VSSQ
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
BA 1
A0
5
DQ 2
DQ 1
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
A1 0
A2
A1
6
DQ 0
VDDQ
VD D
VSS
VSS
VSS
VSS
VSS
VSS
VD D
A1 1
A3
7
DQ 31
VDDQ
VD D
VSS
VSS
VSS
VSS
VSS
VSS
VD D
A9
A4
8
DQ 29
DQ 30
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
NC
A5
A6
9
DQ 28
VDDQ
VSSQ
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
NC
A7
10
VSSQ
NC
VSSQ
VD D
VDDQ
VDDQ
NC
VDDQ
VDDQ
VD D
CL K
A8 /AP
11
DM3
VDDQ
DQ 26
VDDQ
DQ 15
DQ 13
DM1
DQ 11
DQ 9
NC
/CLK
CK E
12
DQS3
DQ 27
DQ 25
DQ 24
DQ 14
DQ 12
DQS1
DQ 10
DQ 8
NC
NC
VREF
PIN DESCRIPTIONS
CLK, /CLK
CKE
/CS
/RAS
/CAS
/WE
DQ 0-31
DM 0-3
: Ma ster Cl ock
: Clock En able
: Ch ip Select
: Ro w Address Strobe
: Column A ddress Strobe
: Write Enab le
: Data I/O
: Write Mask
A0-11
BA 0,1
V
DD
V
DDQ
Vs s
VssQ
DQ S0-3
V
REF
: Address Inpu t
: Ba nk A ddress Inpu t
: Pow er Supply
: Power Supply for Output
: Ground
: Ground for Output
: Data Strobe
: Reference Voltage
Integrated Silicon Solution, Inc. — www.issi.com
Rev.
A
01/14/09
3
IS43R32800
PIN FUNCTIONS
SYMBOL
TYPE
DESCRIPTION
Cl ock: CL K a nd/CLK are differential clock inputs. A ll address and control
input signals are sampled on the crossing of the positive edge of CL K a nd
negative edgeof /CLK . Output (read) data is referenced to the crossings of
CL K a nd /CLK (both directions of crossing).
Cl ock E nable: CK E controls internal clock. W hen CKE is low, internal clock
for the following cycle is ceased. C KE is also used to select auto/ self refresh.
Af ter self refresh mode is started, CK E becomes asynchronous input. Self refresh
is maintained as long as CK E i s low.
Chip Select: W hen /CS is high, any command means No Operation.
Combination of /RA S, /CAS , /WE defines basic commands.
A0-1 1 specify the Row / Column Address in conjunction with BA0,1. T he
Row Address is specifi ed by A0-11. The Column Address is specified by
A0-7 ,A 9. A8 is also used to indicate precharge option. W hen A8 is
high at a read / write command, an auto precharge is performed. When A8
is high at a precharge command, all banks are precharged.
Bank Address: BA 0,1 specifies one of four banks to which a command is
applied. BA 0,1 must be set with ACT, PR E, READ, WR IT E commands.
Data Input/Output: D ata bus
Data Strobe: Outputwith read data, inputwith write data. E dge-aligned
with read data, centered in write data. Used to captu write data.
re
DQS 0 for DQ0 - DQ7, DQS 1 for DQ8 - DQ15, DQS2 for DQ16 - DQ23,
DQS3 for DQ24 - DQ31.
Input Data Mask: DM is an inputmask signal for write data. I nput data
is masked when DM is sampled HIG H along with that input data
during a WR IT E access. DM is sampled on both edges of D QS.
Al though DM pins are input only, the DM loading matches the DQ
andDQS loading. DM 0 for DQ0 - DQ7, DM1 for DQ8 - DQ15,
DM 2 for DQ16 - DQ23, DM 3 for DQ24 - DQ31.
Power Supp for the memory array and peripheral circuitry.
ly
V
DDQ
and Vss
Q
are supplied to the Output Buffers only.
SST L_ 2 reference voltage.
CL K, /CLK
Input
CK E
I nput
/CS
/RAS , /CAS, /WE
I nput
I nput
A0-1 1
Input
BA 0,1
DQ0-31
Input
Input / Output
DQS0- 3
Input / Output
DM0- 3
Input
V
DD
, Vs s
V
DDQ
, Vss
Q
Vref
Power Supp
ly
Power Supp
ly
Input
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev.
A
01/14/09
IS43R32800
FUNCTIONAL DESCRIPTION
ISSI's 256-Mbit DDR SDRAM provides basic functions, bank (row) activate, burst read / write, bank (row)
precharge and auto / self refresh. E ach command is defined by control signals of /RA S, /CAS and
,
/WE at CLK rising edge. I n addition to 3 signals, /CS ,C KE and A8 are usedas chip select, refresh
option, and prechargeoption, respect
ively. To know the detailed definition of commands, please
see the command truth table.
/CLK
CL K
/CS
/RAS
/CAS
/WE
CK E
A8
Chip Select : L =select, H=deselect
Command
Command
Command
Refresh Option @ refresh command
Precharge Option @ precharge or read/write command
define basic commands
Activate ( ACT)
[/RA S =L, /CAS =/WE =H ]
AC T c ommand activates a row in an idle bank indicated by BA .
Read (R EAD)
[/RAS =H , /CA S =L, /WE = H]
RE AD command starts burst read from the active bank indicated by BA . F irst output data appear after
s
/CAS latency. When A8 =H at this command, the bank is deactivated after the burst read (auto-
precharge READ A )
Write (WRITE)
[/RA S =H, /CAS =/WE =L ]
WR IT E c ommand starts burst write to the active bank indicated by BA . T otal data length to be written
is set by burst length. W hen A8 =H at this command, the bank is deactivated after the burst write
(auto-precharge, WRITEA )
Prechar ge (P RE )
[ /RAS =L , /CA S =H, /WE = L]
PR E c ommand deactivates the active bank indicated by BA . T his command also terminates burst read
/write operation. When A8 =H at this command, all banks are deactivated (precharge all, PREA ).
Auto-Ref resh (REFA )
[ /RAS =/CA S =L, /WE = CK E = H]
RE FA command starts auto-refresh cycle. R efresh address including bank address are generated
internally. A fter this command, the banks are precharged automatically.
Integrated Silicon Solution, Inc. — www.issi.com
Rev.
A
01/14/09
5
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参数对比
与IS43R32800-75BL相近的元器件有:IS43R32800-5BL、IS43R32800-6BL。描述及对比如下:
型号 IS43R32800-75BL IS43R32800-5BL IS43R32800-6BL
描述 Synchronous DRAM, 8MX32, 0.75ns, CMOS, PBGA144, 12 X 12 MM, 0.80 MM PITCH, LEAD FREE, FBGA-144 Synchronous DRAM, 8MX32, 0.7ns, CMOS, PBGA144, 12 X 12 MM, 0.80 MM PITCH, LEAD FREE, FBGA-144 Synchronous DRAM, 8MX32, 0.7ns, CMOS, PBGA144, 12 X 12 MM, 0.80 MM PITCH, LEAD FREE, FBGA-144
是否无铅 不含铅 不含铅 不含铅
是否Rohs认证 符合 符合 符合
零件包装代码 BGA BGA BGA
包装说明 LFBGA, BGA144,12X12,32 LFBGA, BGA144,12X12,32 LFBGA, BGA144,12X12,32
针数 144 144 144
Reach Compliance Code compliant compliant compliant
ECCN代码 EAR99 EAR99 EAR99
访问模式 FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST
最长访问时间 0.75 ns 0.7 ns 0.7 ns
其他特性 AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH
最大时钟频率 (fCLK) 133 MHz 200 MHz 166 MHz
I/O 类型 COMMON COMMON COMMON
交错的突发长度 2,4,8 2,4,8 2,4,8
JESD-30 代码 S-PBGA-B144 S-PBGA-B144 S-PBGA-B144
JESD-609代码 e1 e1 e1
长度 12 mm 12 mm 12 mm
内存密度 268435456 bit 268435456 bit 268435456 bit
内存集成电路类型 SYNCHRONOUS DRAM SYNCHRONOUS DRAM SYNCHRONOUS DRAM
内存宽度 32 32 32
湿度敏感等级 3 3 3
功能数量 1 1 1
端口数量 1 1 1
端子数量 144 144 144
字数 8388608 words 8388608 words 8388608 words
字数代码 8000000 8000000 8000000
工作模式 SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
最高工作温度 70 °C 70 °C 70 °C
组织 8MX32 8MX32 8MX32
输出特性 3-STATE 3-STATE 3-STATE
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 LFBGA LFBGA LFBGA
封装等效代码 BGA144,12X12,32 BGA144,12X12,32 BGA144,12X12,32
封装形状 SQUARE SQUARE SQUARE
封装形式 GRID ARRAY, LOW PROFILE, FINE PITCH GRID ARRAY, LOW PROFILE, FINE PITCH GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度) 260 260 260
电源 2.5 V 2.5 V 2.5 V
认证状态 Not Qualified Not Qualified Not Qualified
刷新周期 4096 4096 4096
座面最大高度 1.4 mm 1.4 mm 1.4 mm
自我刷新 YES YES YES
连续突发长度 2,4,8 2,4,8 2,4,8
最大待机电流 0.035 A 0.04 A 0.035 A
最大压摆率 0.36 mA 0.4 mA 0.36 mA
最大供电电压 (Vsup) 2.7 V 2.7 V 2.7 V
最小供电电压 (Vsup) 2.3 V 2.3 V 2.3 V
标称供电电压 (Vsup) 2.5 V 2.5 V 2.5 V
表面贴装 YES YES YES
技术 CMOS CMOS CMOS
温度等级 COMMERCIAL COMMERCIAL COMMERCIAL
端子面层 Tin/Silver/Copper (Sn/Ag/Cu) Tin/Silver/Copper (Sn/Ag/Cu) Tin/Silver/Copper (Sn/Ag/Cu)
端子形式 BALL BALL BALL
端子节距 0.8 mm 0.8 mm 0.8 mm
端子位置 BOTTOM BOTTOM BOTTOM
处于峰值回流温度下的最长时间 40 40 40
宽度 12 mm 12 mm 12 mm
Base Number Matches 1 1 1
厂商名称 - Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI )
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器件捷径:
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ
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