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IS45LV44004-50JA1

EDO DRAM, 4MX4, 50ns, CMOS, PDSO24, 0.300 INCH, SOJ-24

器件类别：存储    存储   

厂商名称：Integrated Silicon Solution ( ISSI )

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参数 预览 参数对比
器件参数
参数名称
属性值
是否无铅
含铅
是否Rohs认证
不符合
厂商名称
Integrated Silicon Solution ( ISSI )
零件包装代码
SOJ
包装说明
0.300 INCH, SOJ-24
针数
24
Reach Compliance Code
compliant
ECCN代码
EAR99
访问模式
FAST PAGE WITH EDO
最长访问时间
50 ns
其他特性
RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH
I/O 类型
COMMON
JESD-30 代码
R-PDSO-J24
JESD-609代码
e0
长度
17.145 mm
内存密度
16777216 bit
内存集成电路类型
EDO DRAM
内存宽度
4
湿度敏感等级
3
功能数量
1
端口数量
1
端子数量
24
字数
4194304 words
字数代码
4000000
工作模式
ASYNCHRONOUS
最高工作温度
85 °C
最低工作温度
-40 °C
组织
4MX4
输出特性
3-STATE
封装主体材料
PLASTIC/EPOXY
封装代码
SOJ
封装等效代码
SOJ24/26,.34
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE
峰值回流温度（摄氏度）
NOT SPECIFIED
电源
3.3 V
认证状态
Not Qualified
刷新周期
4096
座面最大高度
3.556 mm
自我刷新
NO
最大待机电流
0.0005 A
最大压摆率
0.12 mA
最大供电电压 (Vsup)
3.6 V
最小供电电压 (Vsup)
3 V
标称供电电压 (Vsup)
3.3 V
表面贴装
YES
技术
CMOS
温度等级
INDUSTRIAL
端子面层
Tin/Lead (Sn/Pb)
端子形式
J BEND
端子节距
1.27 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
NOT SPECIFIED
宽度
7.62 mm
文档预览
IS45C4400
X
IS45LV4400
X
S
ERIES
4M x 4 (16-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
FEATURES
•
Extended Data-Out (EDO) Page Mode access cycle
•
TTL compatible inputs and outputs
•
Refresh Interval:
2,048 cycles/32 ms
4,096 cycles/64 ms
•
Refresh Mode:
RAS-Only,
CAS-before-RAS
(CBR), and Hidden
ISSI
DESCRIPTION
®
PRELIMINARY INFORMATION
OCTOBER 2002
The
ISSI
4400 Series is a 4,194,304 x 4-bit high-performance
CMOS Dynamic Random Access Memory. These
devices offer an accelerated cycle access called EDO
Page Mode. EDO Page Mode allows 2,048 or 4096
random accesses within a single row with access cycle
time as short as 20 ns per 4-bit word.
These features make the 4400 Series ideally suited for
high-bandwidth graphics, digital signal processing,
high-performance computing systems, and peripheral
applications.
The 4400 Series is packaged in a 24-pin 300-mil SOJ with
JEDEC standard pinouts.
•
Single power supply:
5V±10% or
3.3V ± 10%
•
Byte Write and Byte Read operation via two
CAS
•
Automotive Temperature Range
Option A:
0°C to +70°C
Option A1:
-40°C to +85°C
PRODUCT SERIES OVERVIEW
Part No.
IS45C44002
IS45C44004
IS45LV44002
IS45LV44004
Refresh
2K
4K
2K
4K
Voltage
5V ± 10%
5V ± 10%
3.3V ± 10%
3.3V ± 10%
KEY TIMING PARAMETERS
Parameter
RAS
Access Time (t
RAC
)
CAS
Access Time (t
CAC
)
Column Address Access Time (t
AA
)
EDO Page Mode Cycle Time (t
PC
)
Read/Write Cycle Time (t
RC
)
-50
50
13
25
20
84
-60
60
15
30
25
104
Unit
ns
ns
ns
ns
ns
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00A
10/21/02
1
IS45C4400
X
IS45LV4400
X
S
ERIES
FUNCTIONAL BLOCK DIAGRAM
OE
WE
CAS
CONTROL
LOGIC
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
OE
ISSI
®
CAS
CAS
WE
RAS
RAS
CLOCK
GENERATOR
DATA I/O BUS
REFRESH
COUNTER
DATA I/O BUFFERS
ROW DECODER
RAS
COLUMN DECODERS
SENSE AMPLIFIERS
DQ0-DQ3
MEMORY ARRAY
4,194,304 x 4
ADDRESS
BUFFERS
A0-A10(A11)
TRUTH TABLE
Function
Standby
Read
Write: Word (Early Write)
Read-Write
EDO Page-Mode Read
EDO Page-Mode Write
EDO Page-Mode
Read-Write
Hidden Refresh
RAS-Only
Refresh
CBR Refresh
Note:
1. EARLY WRITE only.
1st
2nd
1st
2nd
1st
2nd
Cycle:
Cycle:
Cycle:
Cycle:
Cycle:
Cycle:
Read
Write
(1)
RAS
H
L
L
L
L
L
L
L
L
L
L→H→L
L→H→L
L
H→L
CAS
H
L
L
L
H→L
H→L
H→L
H→L
H→L
H→L
L
L
H
L
WE
X
H
L
H→L
H
H
L
L
H→L
H→L
H
L
X
X
OE
X
L
X
L→H
L
L
X
X
L→H
L→H
L
X
X
X
Address t
R
/t
C
X
ROW/COL
ROW/COL
ROW/COL
ROW/COL
NA/COL
ROW/COL
NA/COL
ROW/COL
NA/COL
ROW/COL
ROW/COL
ROW/NA
X
DQ
High-Z
D
OUT
D
IN
D
OUT
, D
IN
D
OUT
D
OUT
D
IN
D
IN
D
OUT
, D
IN
D
OUT
, D
IN
D
OUT
D
OUT
High-Z
High-Z
2
IIntegrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00A
10/21/02
IS45C4400
X
IS45LV4400
X
S
ERIES
Functional Description
The IS45C4400x and IS45LV4400x are CMOS DRAMs
optimized for high-speed bandwidth, low power appli-
cations. During READ or WRITE cycles, each bit is uniquely
addressed through the 11 or 12 address bits. These are
entered 11 bits (A0-A10) at a time for the 2K refresh device
or 12 bits (A0-A11) at a time for the 4K refresh device. The
row address is latched by the Row Address Strobe (RAS).
The column address is latched by the Column Address
Strobe (CAS).
RAS
is used to latch the first nine bits and
CAS
is used the latter ten bits.
ISSI
Auto Refresh Cycle
®
To retain data, 2,048 refresh cycles are required in each
32 ms period, or 4,096 refresh cycles are required in
each 64ms period. There are two ways to refresh the
memory:
1. By clocking each of the 2,048 row addresses (A0
through A10) or 4096 row addresses (A0 through
A11) with RAS at least once every 32 ms or 64ms
respectively. Any read, write, read-modify-write or
RAS-only cycle refreshes the addressed row.
2. Using a
CAS-before-RAS
refresh cycle.
CAS-before-RAS
refresh is activated by the falling edge of
RAS,
while
holding
CAS
LOW. In
CAS-before-RAS
refresh cycle,
an internal 9-bit counter provides the row addresses
and the external address inputs are ignored.
CAS-before-RAS
is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Memory Cycle
A memory cycle is initiated by bring
RAS
LOW and it is
terminated by returning both
RAS
and
CAS
HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum t
RAS
time has expired. A new
cycle must not be initiated until the minimum precharge
time t
RP
, t
CP
has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of
CAS
or
OE,
whichever occurs last, while holding
WE
HIGH. The
column address must be held for a minimum time
specified by t
AR
. Data Out becomes valid only when t
RAC
,
t
AA
, t
CAC
and t
OEA
are all satisfied. As a result, the access
time is dependent on the timing relationships between
these parameters.
Power-On
After application of the V
DD
supply, an initial pause of 200
µs is required followed by a minimum of eight initialization
cycles (any combination of cycles containing a
RAS
signal).
During power-on, it is recommended that
RAS
track with
V
DD
or be held at a valid V
IH
to avoid current surges.
Write Cycle
A write cycle is initiated by the falling edge of
CAS
and
WE,
whichever occurs last. The input data must be valid
at or before the falling edge of
CAS
or
WE,
whichever
occurs last.
IIntegrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00A
10/21/02
3
IS45C4400
X
IS45LV4400
X
S
ERIES
PIN CONFIGURATION
24 Pin SOJ
ISSI
24
23
22
21
20
19
18
17
16
15
14
13
GND
DQ3
DQ2
CAS
OE
A9
A8
A7
A6
A5
A4
GND
®
VDD
DQ0
DQ1
WE
RAS
*A11(NC)
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
* A11 is NC for 2K Refresh devices
.
PIN DESCRIPTIONS
A0-A11
A0-A10
DQ0-3
WE
OE
RAS
CAS
V
DD
GND
NC
Address Inputs (4K Refresh)
Address Inputs (2K Refresh)
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Column Address Strobe
Power
Ground
No Connection
4
IIntegrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00A
10/21/02
IS45C4400
X
IS45LV4400
X
S
ERIES
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
T
V
DD
I
OUT
P
D
T
STG
Parameters
Voltage on Any Pin Relative to GND
Supply Voltage
Output Current
Power Dissipation
Storage Temperature
5V
3.3V
5V
3.3V
Rating
–1.0 to +7.0
–0.5 to +4.6
–1.0 to +7.0
–0.5 to +4.6
50
1
–55 to +125
Unit
V
V
mA
W
°C
ISSI
®
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltages are referenced to GND.)
Symbol
V
DD
V
IH
V
IL
T
A
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Temperature Range
5V
3.3V
5V
3.3V
5V
3.3V
Option A:
Option A1:
Min.
4.5
3.0
2.4
2.0
–1.0
–0.3
Typ.
5.0
3.3
—
—
—
—
0 to 70
-40 to 85
Max.
5.5
3.6
V
DD
+ 1.0
V
DD
+ 0.3
0.8
0.8
°C
Unit
V
V
V
CAPACITANCE
(1,2)
Symbol
C
IN
1
C
IN
2
C
IO
Parameter
Input Capacitance: A0-A10(A11)
Input Capacitance:
RAS, CAS, WE, OE
Data Input/Output Capacitance: DQ0-DQ3
Max.
5
7
7
Unit
pF
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25°C, f = 1 MHz.
IIntegrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00A
10/21/02
5
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参数对比
与IS45LV44004-50JA1相近的元器件有：IS45C44004-60JA1、IS45LV44002-50JA1、IS45LV44002-60JA1、IS45LV44002-60JA、IS45LV44002-50JA、IS45LV44004-50JA。描述及对比如下：
型号 IS45LV44004-50JA1 IS45C44004-60JA1 IS45LV44002-50JA1 IS45LV44002-60JA1 IS45LV44002-60JA IS45LV44002-50JA IS45LV44004-50JA
描述 EDO DRAM, 4MX4, 50ns, CMOS, PDSO24, 0.300 INCH, SOJ-24 EDO DRAM, 4MX4, 60ns, CMOS, PDSO24, 0.300 INCH, SOJ-24 EDO DRAM, 4MX4, 50ns, CMOS, PDSO24, 0.300 INCH, SOJ-24 EDO DRAM, 4MX4, 60ns, CMOS, PDSO24, 0.300 INCH, SOJ-24 EDO DRAM, 4MX4, 60ns, CMOS, PDSO24, 0.300 INCH, SOJ-24 EDO DRAM, 4MX4, 50ns, CMOS, PDSO24, 0.300 INCH, SOJ-24 EDO DRAM, 4MX4, 50ns, CMOS, PDSO24, 0.300 INCH, SOJ-24
是否无铅 含铅 含铅 含铅 含铅 含铅 含铅 含铅
是否Rohs认证 不符合 不符合 不符合 不符合 不符合 不符合 不符合
厂商名称 Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI )
零件包装代码 SOJ SOJ SOJ SOJ SOJ SOJ SOJ
包装说明 0.300 INCH, SOJ-24 0.300 INCH, SOJ-24 0.300 INCH, SOJ-24 0.300 INCH, SOJ-24 0.300 INCH, SOJ-24 0.300 INCH, SOJ-24 0.300 INCH, SOJ-24
针数 24 24 24 24 24 24 24
Reach Compliance Code compliant compliant compliant compliant compliant compli compli
ECCN代码 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99
访问模式 FAST PAGE WITH EDO FAST PAGE WITH EDO FAST PAGE WITH EDO FAST PAGE WITH EDO FAST PAGE WITH EDO FAST PAGE WITH EDO FAST PAGE WITH EDO
最长访问时间 50 ns 60 ns 50 ns 60 ns 60 ns 50 ns 50 ns
其他特性 RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH
I/O 类型 COMMON COMMON COMMON COMMON COMMON COMMON COMMON
JESD-30 代码 R-PDSO-J24 R-PDSO-J24 R-PDSO-J24 R-PDSO-J24 R-PDSO-J24 R-PDSO-J24 R-PDSO-J24
JESD-609代码 e0 e0 e0 e0 e0 e0 e0
长度 17.145 mm 17.145 mm 17.145 mm 17.145 mm 17.145 mm 17.145 mm 17.145 mm
内存密度 16777216 bit 16777216 bit 16777216 bit 16777216 bit 16777216 bit 16777216 bi 16777216 bi
内存集成电路类型 EDO DRAM EDO DRAM EDO DRAM EDO DRAM EDO DRAM EDO DRAM EDO DRAM
内存宽度 4 4 4 4 4 4 4
湿度敏感等级 3 3 3 3 3 3 3
功能数量 1 1 1 1 1 1 1
端口数量 1 1 1 1 1 1 1
端子数量 24 24 24 24 24 24 24
字数 4194304 words 4194304 words 4194304 words 4194304 words 4194304 words 4194304 words 4194304 words
字数代码 4000000 4000000 4000000 4000000 4000000 4000000 4000000
工作模式 ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS
最高工作温度 85 °C 85 °C 85 °C 85 °C 70 °C 70 °C 70 °C
最低工作温度 -40 °C -40 °C -40 °C -40 °C - - -
组织 4MX4 4MX4 4MX4 4MX4 4MX4 4MX4 4MX4
输出特性 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 SOJ SOJ SOJ SOJ SOJ SOJ SOJ
封装等效代码 SOJ24/26,.34 SOJ24/26,.34 SOJ24/26,.34 SOJ24/26,.34 SOJ24/26,.34 SOJ24/26,.34 SOJ24/26,.34
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE
峰值回流温度（摄氏度） NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
电源 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 5 V
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
刷新周期 4096 4096 2048 2048 2048 2048 4096
座面最大高度 3.556 mm 3.556 mm 3.556 mm 3.556 mm 3.556 mm 3.556 mm 3.556 mm
自我刷新 NO NO NO NO NO NO NO
最大待机电流 0.0005 A 0.001 A 0.0005 A 0.0005 A 0.0005 A 0.0005 A 0.0005 A
最大压摆率 0.12 mA 0.11 mA 0.12 mA 0.11 mA 0.11 mA 0.12 mA 0.12 mA
最大供电电压 (Vsup) 3.6 V 5.5 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V
最小供电电压 (Vsup) 3 V 4.5 V 3 V 3 V 3 V 3 V 3 V
标称供电电压 (Vsup) 3.3 V 5 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
表面贴装 YES YES YES YES YES YES YES
技术 CMOS CMOS CMOS CMOS CMOS CMOS CMOS
温度等级 INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL COMMERCIAL COMMERCIAL COMMERCIAL
端子面层 Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
端子形式 J BEND J BEND J BEND J BEND J BEND J BEND J BEND
端子节距 1.27 mm 1.27 mm 1.27 mm 1.27 mm 1.27 mm 1.27 mm 1.27 mm
端子位置 DUAL DUAL DUAL DUAL DUAL DUAL DUAL
处于峰值回流温度下的最长时间 NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
宽度 7.62 mm 7.62 mm 7.62 mm 7.62 mm 7.62 mm 7.62 mm 7.62 mm
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