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IS61LPS25618A-200B2I

Cache SRAM, 256KX18, 3.1ns, CMOS, PBGA119, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-119

器件类别：存储    存储   

厂商名称：Integrated Silicon Solution ( ISSI )

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器件参数
参数名称
属性值
是否无铅
含铅
是否Rohs认证
不符合
厂商名称
Integrated Silicon Solution ( ISSI )
零件包装代码
BGA
包装说明
BGA, BGA119,7X17,50
针数
119
Reach Compliance Code
compliant
ECCN代码
3A991.B.2.A
Factory Lead Time
10 weeks
最长访问时间
3.1 ns
其他特性
PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)
200 MHz
I/O 类型
COMMON
JESD-30 代码
R-PBGA-B119
JESD-609代码
e0
长度
22 mm
内存密度
4718592 bit
内存集成电路类型
CACHE SRAM
内存宽度
18
湿度敏感等级
3
功能数量
1
端子数量
119
字数
262144 words
字数代码
256000
工作模式
SYNCHRONOUS
最高工作温度
85 °C
最低工作温度
-40 °C
组织
256KX18
输出特性
3-STATE
封装主体材料
PLASTIC/EPOXY
封装代码
BGA
封装等效代码
BGA119,7X17,50
封装形状
RECTANGULAR
封装形式
GRID ARRAY
并行/串行
PARALLEL
峰值回流温度（摄氏度）
NOT SPECIFIED
电源
2.5/3.3,3.3 V
认证状态
Not Qualified
座面最大高度
2.41 mm
最大待机电流
0.000075 A
最小待机电流
3.14 V
最大压摆率
0.21 mA
最大供电电压 (Vsup)
3.465 V
最小供电电压 (Vsup)
3.135 V
标称供电电压 (Vsup)
3.3 V
表面贴装
YES
技术
CMOS
温度等级
INDUSTRIAL
端子面层
Tin/Lead (Sn/Pb)
端子形式
BALL
端子节距
1.27 mm
端子位置
BOTTOM
处于峰值回流温度下的最长时间
NOT SPECIFIED
宽度
14 mm
Base Number Matches
1
文档预览
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
128K x 32, 128K x 36, 256K x 18
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Burst sequence control using MODE input
• Three chip enable option for simple depth ex-
pansion and address pipelining
• Common data inputs and data outputs
• Auto Power-down during deselect
• Single cycle deselect
• Snooze MODE for reduced-power standby
• Power Supply
LPS: V
dd
3.3V + 5%,
V
ddq
3.3V/2.5V + 5%
VPS: V
dd
2.5V + 5%,
V
ddq
2.5V + 5%
• JEDEC 100-Pin QFP, 119-ball and 165-ball
BGA packages
• Automotive temperature available
• Lead Free available
DECEMBER 2013
4 Mb SYNCHRONOUS PIPELINED, SINgLE CYCLE DESELECT STATIC RAM
DESCRIPTION
The
ISSI
IS61(64)LPS12832A, IS61(64)LPS/VP-
S12836A and IS61(64)LPS/VPS25618A are
high-speed,
low-power synchronous static
RAMs
designed to provide
burstable, high-performance memory for communication
and networking applications. The IS61(64)LPS12832A
is
organized as 131,072 words by 32 bits.
The IS61(64)LPS/
VPS12836A is organized as 131,072 words by 36 bits.
The IS61(64)LPS/VPS25618A
is organized as 262,144
words by 18 bits. Fabricated with
ISSI
's advanced CMOS
technology, the device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit. All synchronous inputs pass
through registers controlled by a positive-edge-triggered
single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
The byte write operation is performed by using the byte
write enable (BWE) input combined with one or more
individual byte write signals (BWx).
In addition, Global
Write (GW)
is available for writing all bytes at one time,
regardless of the byte write controls.
Bursts can be initiated with either ADSP
(Address Status
Processor) or
ADSC
(Address Status Cache Controller)
input pins. Subsequent burst addresses can be gener-
ated internally and controlled by the
ADV
(burst address
advance) input pin.
The mode pin is used to select the burst sequence or-
der, Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH
or left floating.
FAST ACCESS TIME
Symbol
t
kq
t
kc
Parameter
Clock Access Time
Cycle Time
Frequency
250
2.6
4
250
200
3.1
5
200
Units
ns
ns
MHz
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liabil-
ity arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.
Rev. H1
12/06/2013
1
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
BLOCK DIAGRAM
MODE
CLK
CLK
Q0
A0
A0'
BINARY
COUNTER
ADV
ADSC
ADSP
CE
CLR
Q1
A1
A1'
128Kx32;
128Kx36;
256Kx18
MEMORY ARRAY
17/18
A
17/18
D
Q
15/16
ADDRESS
REGISTER
CE
CLK
32, 36,
or 18
32, 36,
or 18
GW
BWE
BW(a-d)
x18: a,b
x32/x36: a-d
DQ(a-d)
BYTE WRITE
REGISTERS
CLK
D
Q
CE
CE2
CE2
D
Q
2/4/8
ENABLE
REGISTER
CE
CLK
INPUT
REGISTERS
CLK
OUTPUT
REGISTERS
CLK
32, 36,
or 18
DQa - DQd
OE
D
Q
ZZ
POWER
DOWN
ENABLE
DELAY
REGISTER
CLK
OE
2
Integrated Silicon Solution, Inc.
Rev. H1
12/06/2013
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
165-PIN BgA
165-Ball, 13x15 mm BGA
1mm Ball Pitch, 11x15 Ball Array
119-PIN BgA
119-Ball, 14x22 mm BGA
1mm Ball Pitch, 7x17 Ball Array
BOTTOM VIEW
BOTTOM VIEW
Integrated Silicon Solution, Inc.
Rev. H1
12/06/2013
3
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
119 BGA PACKAGE PIN CONFIGURATION
128k
x
36 (TOP VIEW)
1
A
B
C
D
E
F
g
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQc
DQc
V
DDQ
DQc
DQc
V
DDQ
DQd
DQd
V
DDQ
DQd
DQd
NC
NC
V
DDQ
2
A
CE2
A
DQPc
DQc
DQc
DQc
DQc
V
DD
DQd
DQd
DQd
DQd
DQPd
A
NC
NC
3
A
A
A
Vss
Vss
Vss
BWc
Vss
NC
Vss
BWd
Vss
Vss
Vss
MODE
A
NC
4
ADSP
ADSC
V
DD
NC
CE
OE
ADV
GW
V
DD
CLK
NC
BWE
A
1
*
A
0
*
V
DD
A
NC
5
A
A
A
Vss
Vss
Vss
BWb
Vss
NC
Vss
BWa
Vss
Vss
Vss
NC
A
NC
6
A
CE2
A
DQPb
DQb
DQb
DQb
DQb
V
DD
DQa
DQa
DQa
DQa
DQPa
A
NC
NC
7
V
DDQ
NC
NC
DQb
DQb
V
DDQ
DQb
DQb
V
DDQ
DQa
DQa
V
DDQ
DQa
DQa
NC
ZZ
V
DDQ
Note:
* A
0
and A
1
are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
ADSP
ADSC
GW
CLK
CE, CE2, CE2
BWx (x=a-d)
BWE
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address
Advance
Address Status Processor
Address Status Controller
Global Write Enable
Synchronous Clock
Synchronous Chip Select
Synchronous Byte Write Controls
Byte Write Enable
Symbol
OE
ZZ
MODE
NC
DQa-DQd
DQPa-Pd
V
dd
V
ddq
Vss
Pin Name
Output Enable
Power Sleep Mode
Burst Sequence Selection
No Connect
Data Inputs/Outputs
Output Power Supply
Power Supply
Output Power Supply
Ground
4
Integrated Silicon Solution, Inc.
Rev. H1
12/06/2013
IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
119 BGA PACKAGE PIN CONFIGURATION
256k
x
18 (TOP VIEW)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VDDQ
NC
NC
DQb
NC
VDDQ
NC
DQb
VDDQ
NC
DQb
VDDQ
DQb
NC
NC
NC
VDDQ
2
A
CE2
A
NC
DQb
NC
DQb
NC
VDD
DQb
NC
DQb
NC
DQPb
A
A
NC
3
A
A
A
Vss
Vss
Vss
BWb
Vss
NC
Vss
Vss
Vss
Vss
Vss
MODE
A
NC
4
ADSP
ADSC
VDD
NC
CE
OE
ADV
GW
VDD
CLK
NC
BWE
A1*
A0*
VDD
NC
NC
5
A
A
A
Vss
Vss
Vss
Vss
Vss
NC
Vss
BWa
Vss
Vss
Vss
NC
A
NC
6
A
CE2
A
DQPa
NC
DQa
NC
DQa
VDD
NC
DQa
NC
DQa
NC
A
A
NC
7
VDDQ
NC
NC
NC
DQa
VDDQ
DQa
NC
VDDQ
DQa
NC
VDDQ
NC
DQa
NC
ZZ
VDDQ
Note:
* A
0
and A
1
are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
ADSP
ADSC
GW
CLK
CE, CE2, CE2
BWx (x=a,b)
BWE
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address
Advance
Address Status Processor
Address Status Controller
Global Write Enable
Synchronous Clock
Synchronous Chip Select
Synchronous Byte Write Controls
Byte Write Enable
Symbol
OE
ZZ
MODE
NC
DQa-DQb
DQPa-Pb
V
dd
V
ddq
Vss
Pin Name
Output Enable
Power Sleep Mode
Burst Sequence Selection
No Connect
Data Inputs/Outputs
Output Power Supply
Power Supply
Output Power Supply
Ground
Integrated Silicon Solution, Inc.
Rev. H1
12/06/2013
5
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参数对比
与IS61LPS25618A-200B2I相近的元器件有：IS61LPS12836A-200B2I、IS61LPS25618A-200TQI、IS61LPS25618A-200TQLI、IS61LPS12836A-200TQLI、IS61LPS12836A-200B2LI、IS61LPS12836A-200TQI。描述及对比如下：
型号 IS61LPS25618A-200B2I IS61LPS12836A-200B2I IS61LPS25618A-200TQI IS61LPS25618A-200TQLI IS61LPS12836A-200TQLI IS61LPS12836A-200B2LI IS61LPS12836A-200TQI
描述 Cache SRAM, 256KX18, 3.1ns, CMOS, PBGA119, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-119 Cache SRAM, 128KX36, 3.1ns, CMOS, PBGA119, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-119 256KX18 CACHE SRAM, 3.1ns, PQFP100, TQFP-100 Cache SRAM, 256KX18, 3.1ns, CMOS, PQFP100, LEAD FREE, TQFP-100 Cache SRAM, 128KX36, 3.1ns, CMOS, PQFP100, LEAD FREE, TQFP-100 Cache SRAM, 128KX36, 3.1ns, CMOS, PBGA119, 14 X 22 MM, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-119 128KX36 CACHE SRAM, 3.1ns, PQFP100, TQFP-100
是否无铅 含铅 含铅 含铅 不含铅 不含铅 不含铅 含铅
是否Rohs认证 不符合 不符合 不符合 符合 符合 符合 不符合
零件包装代码 BGA BGA QFP QFP QFP BGA QFP
包装说明 BGA, BGA119,7X17,50 BGA, BGA119,7X17,50 TQFP-100 LQFP, QFP100,.63X.87 LQFP, QFP100,.63X.87 BGA, BGA119,7X17,50 TQFP-100
针数 119 119 100 100 100 119 100
Reach Compliance Code compliant compli compliant compliant compliant compliant compli
ECCN代码 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991 3A991.B.2.A 3A991.B.2.A
最长访问时间 3.1 ns 3.1 ns 3.1 ns 3.1 ns 3.1 ns 3.1 ns 3.1 ns
其他特性 PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE
最大时钟频率 (fCLK) 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz
I/O 类型 COMMON COMMON COMMON COMMON COMMON COMMON COMMON
JESD-30 代码 R-PBGA-B119 R-PBGA-B119 R-PQFP-G100 R-PQFP-G100 R-PQFP-G100 R-PBGA-B119 R-PQFP-G100
JESD-609代码 e0 e0 e0 e3 e3 e1 e0
长度 22 mm 22 mm 20 mm 20 mm 20 mm 22 mm 20 mm
内存密度 4718592 bit 4718592 bi 4718592 bit 4718592 bit 4718592 bit 4718592 bit 4718592 bi
内存集成电路类型 CACHE SRAM CACHE SRAM CACHE SRAM CACHE SRAM CACHE SRAM CACHE SRAM CACHE SRAM
内存宽度 18 36 18 18 36 36 36
湿度敏感等级 3 3 3 3 3 3 3
功能数量 1 1 1 1 1 1 1
端子数量 119 119 100 100 100 119 100
字数 262144 words 131072 words 262144 words 262144 words 131072 words 131072 words 131072 words
字数代码 256000 128000 256000 256000 128000 128000 128000
工作模式 SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
最高工作温度 85 °C 85 °C 85 °C 85 °C 85 °C 85 °C 85 °C
最低工作温度 -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C
组织 256KX18 128KX36 256KX18 256KX18 128KX36 128KX36 128KX36
输出特性 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 BGA BGA LQFP LQFP LQFP BGA LQFP
封装等效代码 BGA119,7X17,50 BGA119,7X17,50 QFP100,.63X.87 QFP100,.63X.87 QFP100,.63X.87 BGA119,7X17,50 QFP100,.63X.87
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 GRID ARRAY GRID ARRAY FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE GRID ARRAY FLATPACK, LOW PROFILE
并行/串行 PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL
峰值回流温度（摄氏度） NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED 260 260 260 NOT SPECIFIED
电源 2.5/3.3,3.3 V 2.5/3.3,3.3 V 2.5/3.3,3.3 V 2.5/3.3,3.3 V 2.5/3.3,3.3 V 2.5/3.3,3.3 V 2.5/3.3,3.3 V
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
座面最大高度 2.41 mm 2.41 mm 1.6 mm 1.6 mm 1.6 mm 2.41 mm 1.6 mm
最大待机电流 0.000075 A 0.075 A 0.000075 A 0.000075 A 0.075 A 0.075 A 0.075 A
最小待机电流 3.14 V 3.14 V 3.14 V 3.14 V 3.14 V 3.14 V 3.14 V
最大压摆率 0.21 mA 0.21 mA 0.21 mA 0.21 mA 0.21 mA 0.21 mA 0.21 mA
最大供电电压 (Vsup) 3.465 V 3.465 V 3.465 V 3.465 V 3.465 V 3.465 V 3.465 V
最小供电电压 (Vsup) 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V
标称供电电压 (Vsup) 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
表面贴装 YES YES YES YES YES YES YES
技术 CMOS CMOS CMOS CMOS CMOS CMOS CMOS
温度等级 INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL
端子面层 Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed Tin/Silver/Copper (Sn/Ag/Cu) Tin/Lead (Sn/Pb)
端子形式 BALL BALL GULL WING GULL WING GULL WING BALL GULL WING
端子节距 1.27 mm 1.27 mm 0.65 mm 0.65 mm 0.65 mm 1.27 mm 0.65 mm
端子位置 BOTTOM BOTTOM QUAD QUAD QUAD BOTTOM QUAD
处于峰值回流温度下的最长时间 NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED 40 10 40 NOT SPECIFIED
宽度 14 mm 14 mm 14 mm 14 mm 14 mm 14 mm 14 mm
厂商名称 Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI ) - Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI )
Factory Lead Time 10 weeks 10 weeks 12 weeks 10 weeks - 10 weeks 12 weeks
Base Number Matches 1 1 1 1 1 - -
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器件捷径:
00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W
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