IS61LV5128
512K x 8 HIGH-SPEED CMOS STATIC RAM
FEATURES
• High-speed access times:
10, 12 and 15 ns
• High-performance, low-power CMOS process
• Multiple center power and ground pins for
greater noise immunity
• Easy memory expansion with
CE
and
OE
options
•
CE
power-down
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 3.3V power supply
• Packages available:
– 36-pin 400-mil SOJ
– 36-pin miniBGA
– 44-pin TSOP (Type II)
ISSI
®
JULY 2001
DESCRIPTION
The
ISSI
IS61LV5128 is a very high-speed, low power,
524,288-word by 8-bit CMOS static RAM. The IS61LV5128
is fabricated using
ISSI
's high-performance CMOS tech-
nology. This highly reliable process coupled with innova-
tive circuit design techniques, yields higher performance
and low power consumption devices.
When
CE
is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 250 µW (typical) with CMOS input levels.
The IS61LV5128 operates from a single 3.3V power
supply and all inputs are TTL-compatible.
The IS61LV5128 is available in 36-pin 400-mil SOJ, 36-
pin mini BGA, and 44-pin TSOP (Type II) packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A18
DECODER
512K X 8
MEMORY ARRAY
VCC
GND
I/O
DATA
CIRCUIT
I/O0-I/O7
COLUMN I/O
CE
OE
WE
CONTROL
CIRCUIT
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
07/16/01
1
IS61LV5128
PIN CONFIGURATION
36 mini BGA
44-Pin TSOP (Type II)
ISSI
2
3
4
5
6
®
1
A
B
C
D
E
F
G
H
A0
I/O4
I/O5
GND
Vcc
I/O6
I/O7
A9
A1
A2
NC
WE
NC
A3
A4
A5
A6
A7
A8
I/O0
I/O1
Vcc
GND
A18
OE
A10
CE
A11
A17
A16
A12
A15
A13
I/O2
I/O3
A14
NC
NC
A0
A1
A2
A3
A4
CE
I/O0
I/O1
Vcc
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
A18
A17
A16
A15
OE
I/O7
I/O6
GND
Vcc
I/O5
I/O4
A14
A13
A12
A11
A10
NC
NC
NC
PIN DESCRIPTIONS
A0-A18
CE
OE
WE
I/O0-I/O7
Vcc
GND
NC
Address Inputs
Chip Enable Input
Output Enable Input
Write Enable Input
Bidirectional Ports
Power
Ground
No Connection
36-Pin SOJ
A0
A1
A2
A3
A4
CE
I/O0
I/O1
Vcc
GND
I/O2
I/O3
WE
A5
A6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A18
A17
A16
A15
OE
I/O7
I/O6
GND
Vcc
I/O5
I/O4
A14
A13
A12
A11
A10
NC
TRUTH TABLE
Mode
WE
CE
H
L
L
L
OE
X
H
L
X
I/O Operation Vcc Current
High-Z
High-Z
D
OUT
D
IN
I
SB
1
, I
SB
2
I
CC
I
CC
I
CC
Not Selected
X
(Power-down)
Output Disabled H
Read
H
Write
L
A7
A8
A9
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
07/16/01
IS61LV5128
ISSI
Value
–0.5 to Vcc + 0.5
–55 to +125
–65 to +150
1.0
Unit
V
°C
°C
W
®
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
BIAS
T
STG
P
T
Parameter
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-
nent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
10 ns
V
CC
3.3V +10%, -5%
3.3V +10%, -5%
12 ns, 15 ns
V
CC
3.3V ± 10%
3.3V ± 10%
CAPACITANCE
(1,2)
Symbol
C
IN
C
I/O
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
6
8
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25°C, f = 1 MHz, Vcc = 3.3V.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
07/16/01
3
IS61LV5128
ISSI
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
Min.
2.4
—
2.0
–0.3
GND
≤
V
IN
≤
V
CC
GND
≤
V
OUT
≤
V
CC
, Outputs Disabled
Com.
Ind.
Com.
Ind.
–1
–5
–1
–5
Max.
—
0.4
V
CC
+ 0.3
0.8
1
5
1
5
Unit
V
V
V
V
µA
µA
®
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol Parameter
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
(1)
Input Leakage
Output Leakage
Note:
1. V
IL
= –3.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
Symbol Parameter
I
CC
I
SB
Vcc Operating
Supply Current
TTL Standby
Current
(TTL Inputs)
TTL Standby
Current
(TTL Inputs)
CMOS Standby
Current
(CMOS Inputs)
Test Conditions
V
CC
= Max.,
CE
= V
IL
I
OUT
= 0 mA, f = f
MAX
.
V
CC
= Max.,
V
IN
= V
IH
or V
IL
CE
≥
V
IH
, f = f
MAX
.
V
CC
= Max.,
V
IN
= V
IH
or V
IL
CE
≥
V
IH
, f = 0
V
CC
= Max.,
CE
≤
V
CC
– 0.2V,
V
IN
≥
V
CC
– 0.2V, or
V
IN
≤
0.2V, f = 0
Com.
Ind.
Com.
Ind.
Com.
Ind.
Com.
Ind.
-10 ns
Min.
Max.
—
—
—
—
—
—
—
—
145
155
70
80
20
25
10
15
-12 ns
Min.
Max.
—
—
—
—
—
—
—
—
135
145
60
70
20
25
10
15
-15 ns
Min.
Max.
—
—
—
—
—
—
—
—
125
135
50
60
20
25
10
15
Unit
mA
mA
I
SB
1
mA
I
SB
2
mA
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
07/16/01
IS61LV5128
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
Symbol
Parameter
Read Cycle Time
Address Access Time
Output Hold Time
CE
Access Time
OE
Access Time
OE
to Low-Z Output
OE
to High-Z Output
CE
to Low-Z Output
CE
to High-Z Output
Power Up Time
Power Down Time
-10 ns
Min.
Max.
10
—
3
—
—
0
0
3
0
0
—
—
10
—
10
4
—
4
—
4
—
10
-12 ns
Min.
Max.
12
—
3
—
—
0
0
3
0
0
—
—
12
—
12
5
—
5
—
6
—
12
ISSI
-15 ns
Min.
Max.
15
—
3
—
—
0
0
3
0
0
—
—
15
—
15
7
—
6
—
8
—
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
®
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
(2)
t
HZOE
(2)
t
LZCE
(2)
t
HZCE
(2)
t
PU
t
PD
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
319
Ω
3.3V
3.3V
319
Ω
OUTPUT
30 pF
Including
jig and
scope
353
Ω
OUTPUT
5 pF
Including
jig and
scope
353
Ω
Figure 1
Figure 2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
07/16/01
5
