ity arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. E
10/25/2013
1
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
BLOCK DIAGRAM
x 72: A [0:17] or
x 36: A [0:18] or
x 18: A [0:19]
ADDRESS
REGISTER
A2-A17 or A2-A18 or A2-A19
256Kx72; 512Kx36;
1024Kx18
MEMORY ARRAY
MODE
A0-A1
BURST
ADDRESS
COUNTER
A'0-A'1
K
DATA-IN
REGISTER
CLK
CKE
CONTROL
LOGIC
K
WRITE
ADDRESS
REGISTER
WRITE
ADDRESS
REGISTER
K
DATA-IN
REGISTER
CE
CE2
CE2
ADV
WE
BWŸ
X
OE
ZZ
DQx/DQPx
}
CONTROL
REGISTER
CONTROL
LOGIC
K
(X=a-h, a-d, or a,b)
BUFFER
72, 36 or 18
2
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. E
10/25/2013
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
165-Ball, 13 mm x 15mm BGA
Bottom View
209-Ball, 14 mm x 22 mm BGA
Bottom View
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. E
10/25/2013
3
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
PIN CONFIGURATION — 256K x 72, 209-Ball PBGA (TOP VIEW)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
1
DQg
DQg
DQg
DQg
DQPg
DQc
DQc
DQc
DQc
NC
DQh
DQh
DQh
DQh
DQPd
DQd
DQd
DQd
DQd
2
DQg
DQg
DQg
DQg
DQPc
DQc
DQc
DQc
DQc
NC
DQh
DQh
DQh
DQh
DQPh
DQd
DQd
DQd
DQd
3
A
BWc
BWh
V
SS
V
ddq
V
SS
V
ddq
V
SS
V
ddq
CLK
V
ddq
V
SS
V
ddq
V
SS
V
ddq
V
SS
NC
A
TMS
4
CE2
BWg
BWd
NC
V
ddq
V
SS
V
ddq
V
SS
V
ddq
NC
V
ddq
V
SS
V
ddq
V
SS
V
ddq
NC
A
A
TDI
5
A
NC
NC
NC
V
dd
V
SS
V
dd
V
SS
V
dd
V
SS
V
dd
V
SS
V
dd
V
SS
V
dd
NC
NC
A
A
6
ADV
WE
CE
OE
V
dd
NC
NC
NC
NC
CKE
NC
NC
NC
ZZ
V
dd
MODE
A
A1
A0
7
A
A
NC
NC
V
dd
V
SS
V
dd
V
SS
V
dd
V
SS
V
dd
V
SS
V
dd
V
SS
V
dd
NC
NC
A
A
8
CE2
BWb
BWe
NC
V
ddq
V
SS
V
ddq
V
SS
V
ddq
NC
V
ddq
V
SS
V
ddq
V
SS
V
ddq
NC
A
A
TDO
9
A
BWf
BWa
V
SS
V
ddq
V
SS
V
ddq
V
SS
V
ddq
NC
V
ddq
V
SS
V
ddq
V
SS
V
ddq
V
SS
NC
A
TCK
10
DQb
DQb
DQb
DQb
DQPf
DQf
DQf
DQf
DQf
NC
DQa
DQa
DQa
DQa
DQPa
DQe
DQe
DQe
DQe
11
DQb
DQb
DQb
DQb
DQPb
DQf
DQf
DQf
DQf
NC
DQa
DQa
DQa
DQa
DQPe
DQe
DQe
DQe
DQe
11 x 19 Ball BGA—14 x 22 mm
2
Body—1 mm Ball Pitch
PIN DESCRIPTIONS
Symbol
A
A0, A1
Pin Name
Synchronous Address Inputs
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
ADV
Synchronous Burst Address Advance
BWa-BWh
Synchronous Byte Write Enable
CE, CE2,
CE2 Synchronous Chip Enable
CLK
Synchronous Clock
CKE
Clock Enable
DQx
Synchronous Data Input/Output
DQPx
Parity Data I/O
V
SS
MODE
OE
TCK, TDI
TDO, TMS
V
dd
V
ddq
WE
ZZ
Ground
Burst Sequence Selection
Output Enable
JTAG Pins
3.3V/2.5V Power Supply
Isolated Output Buffer Supply:
3.3V/2.5V
Write Enable
Snooze Enable
4
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. E
10/25/2013
IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
PIN CONFIGURATION — 512K
x
36, 165-Ball PBGA (TOP VIEW)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
NC
DQPc
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
DQPd
NC
MODE
2
A
A
NC
DQc
DQc
DQc
DQc
VDD
DQd
DQd
DQd
DQd
NC
NC
NC
3
CE
CE2
V
ddq
V
ddq
V
ddq
V
ddq
V
ddq
NC
V
ddq
V
ddq
V
ddq
V
ddq
V
ddq
A
A
4
BWc
BWd
V
SS
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
SS
A
A
5
BWb
BWa
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TdI
TMS
6
CE2
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1*
A0*
7
CKE
WE
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCK
8
ADV
OE
V
SS
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
SS
A
A
9
A
A
V
ddq
V
ddq
V
ddq
V
ddq
V
ddq
NC
V
ddq
V
ddq
V
ddq
V
ddq
V
ddq
A
A
10
A
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
A
11
NC
NC
DQPb
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
DQPa
NC
A
Note:
A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
WE
CLK
CKE
CE
CE2
CE2
BWx (x=a-d)
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address Advance/
Load
Synchronous Read/Write Control
Input
Synchronous Clock
Clock Enable
Synchronous Chip Select
Synchronous Chip Select
Synchronous Chip Select
Synchronous Byte Write Inputs
Symbol
OE
ZZ
MODE
TCK, TDI
TDO, TMS
V
DD
NC
DQx
DQPx
V
DDQ
V
SS
Pin Name
Output Enable
Power Sleep Mode
Burst Sequence Selection
JTAG Pins
3.3V/2.5V Power Supply
No Connect
Data Inputs/Outputs
Parity Data I/O
Isolated output Power Supply
3.3V/2.5V
Ground
Integrated Silicon Solution, Inc. — www.issi.com —
