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IS61NLP102436A/IS61NVP102436A

IS61NLP204818A/IS61NVP204818A

1Mb x 36 and 2Mb x 18

36Mb, PIPELINE 'NO WAIT' STATE BUS SRAM

SEPTEMBER 2007

FEATURES

• 100 percent bus utilization

• No wait cycles between Read and Write

• Internal self-timed write cycle

• Individual Byte Write Control

• Single R/W (Read/Write) control pin

• Clock controlled, registered address,

data and control

• Interleaved or linear burst sequence control using

MODE input

• Three chip enables for simple depth expansion

and address pipelining

• Power Down mode

• Common data inputs and data outputs

•

CKE

pin to enable clock and suspend operation

• JEDEC 100-pin TQFP and 165-ball PBGA

packages

• Power supply:

NVP: V

2.5V (± 5%), V

DDQ

2.5V (± 5%)

NLP: V

3.3V (± 5%), V

DDQ

3.3V/2.5V (± 5%)

• Industrial temperature available

• Lead-free available

DESCRIPTION

The 36 Meg 'NLP/NVP' product family feature high-speed,

low-power synchronous static RAMs designed to provide

a burstable, high-performance, 'no wait' state, device for

networking and communications applications. They are

organized as 1M words by 36 bits and 2M words by 18 bits,

fabricated with

ISSI

's advanced CMOS technology.

Incorporating a 'no wait' state feature, wait cycles are

eliminated when the bus switches from read to write, or

write to read. This device integrates a 2-bit burst counter,

high-speed SRAM core, and high-drive capability outputs

into a single monolithic circuit.

All synchronous inputs pass through registers are controlled

by a positive-edge-triggered single clock input. Operations

may be suspended and all synchronous inputs ignored

when Clock Enable,

CKE

is HIGH. In this state the internal

device will hold their previous values.

All Read, Write and Deselect cycles are initiated by the

ADV input. When the ADV is HIGH the internal burst

counter is incremented. New external addresses can be

loaded when ADV is LOW.

Write cycles are internally self-timed and are initiated by

the rising edge of the clock inputs and when

is LOW.

Separate byte enables allow individual bytes to be written.

A burst mode pin (MODE) defines the order of the burst

sequence. When tied HIGH, the interleaved burst sequence

is selected. When tied LOW, the linear burst sequence is

selected.

FAST ACCESS TIME

Symbol

Parameter

Clock Access Time

Cycle Time

Frequency

-200

3.1

200

-166

3.5

166

Units

MHz

Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability

arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any

published information and before placing orders for products.

Integrated Silicon Solution, Inc.

Rev. A

09/13/07

IS61NLP102436A/IS61NVP102436A

IS61NLP204818A/IS61NVP204818A

BLOCK DIAGRAM

x 36: A [0:19] or

x 18: A [0:20]

ADDRESS

A2-A19 or A2-A20

1Mx36;

2Mx18

MEMORY ARRAY

MODE

A0-A1

BURST

ADDRESS

COUNTER

A'0-A'1

DATA-IN

CLK

CKE

CE2

ADV

BWŸ

CONTROL

LOGIC

WRITE

ADDRESS

WRITE

ADDRESS

DATA-IN

}

CONTROL

LOGIC

OUTPUT

BUFFER

(X=a,b,c,d or a,b)

36 or 18

DQx/DQPx

Integrated Silicon Solution, Inc. — www.issi.com

Rev. A

09/13/07

IS61NLP102436A/IS61NVP102436A

IS61NLP204818A/IS61NVP204818A

PIN CONFIGURATION — 1M

36, 165-Ball PBGA (TOP VIEW)

DQPc

DQc

DQd

DQPd

MODE

DQc

DQd

CE2

DDQ

BWc

BWd

BWb

BWa

CE2

CLK

A1*

A0*

CKE

ADV

DDQ

DQb

DQa

DQPb

DQb

DQa

DQPa

Note:

A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.

(Under Evaluation)

PIN DESCRIPTIONS

Symbol

A0, A1

ADV

CLK

CKE

BWx

(x=a-d)

Pin Name

Address Inputs

Synchronous Burst Address Inputs

Synchronous Burst Address Advance/

Load

Synchronous Read/Write Control

Input

Synchronous Clock

Clock Enable

Synchronous Byte Write Inputs

Output Enable

Power Sleep Mode

MODE

DQx

DQPx

DDQ

Burst Sequence Selection

3.3V/2.5V Power Supply

No Connect

Data Inputs/Outputs

Parity Data I/O

Isolated output Power Supply

3.3V/2.5V

Ground

CE, CE2,

CE2 Synchronous Chip Enable

Integrated Silicon Solution, Inc. — www.issi.com

Rev. A

09/13/07

IS61NLP102436A/IS61NVP102436A

IS61NLP204818A/IS61NVP204818A

165-PIN PBGA PACKAGE CONFIGURATION

2M x 18 (TOP VIEW)

DQb

DQPb

MODE

DQb

CE2

DDQ

BWb

Vss

BWa

Vss

CE2

CLK

Vss

CKE

Vss

ADV

Vss

DDQ

DQa

DQPa

DQa

Note:

A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.

(Under Evaluation)

PIN DESCRIPTIONS

Symbol

A0, A1

ADV

CLK

CKE

BWx

(x=a,b)

Pin Name

Address Inputs

Synchronous Burst Address Inputs

Synchronous Burst Address Advance/

Load

Synchronous Read/Write Control

Input

Synchronous Clock

Clock Enable

Synchronous Byte Write Inputs

Output Enable

Power Sleep Mode

MODE

DQx

DQPx

DDQ

Burst Sequence Selection

3.3V/2.5V Power Supply

No Connect

Data Inputs/Outputs

Parity Data I/O

Isolated output Power Supply

3.3V/2.5V

Ground

CE, CE2,

CE2 Synchronous Chip Enable

Integrated Silicon Solution, Inc. — www.issi.com

Rev. A

09/13/07

IS61NLP102436A/IS61NVP102436A

IS61NLP204818A/IS61NVP204818A

PIN CONFIGURATION

100-Pin TQFP

BWd

BWc

BWb

BWa

CKE

ADV

CLK

CE2

Vss

BWb

BWa

CKE

ADV

CE2

Vss

CLK

DQPc

DQc

DDQ

Vss

DQc

Vss

DDQ

DQc

VDD

Vss

DQd

DDQ

Vss

DQd

Vss

DDQ

DQd

DQPd

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

MODE

Vss

DQPb

DQb

DDQ

Vss

DQb

Vss

DDQ

DQb

Vss

DQa

DDQ

Vss

DQa

Vss

DDQ

DQa

DQPa

DDQ

Vss

DQb

Vss

DDQ

DQb

VDD

Vss

DQb

DDQ

Vss

DQb

DQPb

Vss

DDQ

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

MODE

Vss

DDQ

Vss

DQPa

DQa

Vss

DDQ

DQa

Vss

DQa

DDQ

Vss

DQa

Vss

DDQ

1M x 36

PIN DESCRIPTIONS

A0, A1

Synchronous Address Inputs. These

pins must tied to the two LSBs of the

address bus.

Synchronous Address Inputs

Synchronous Clock

Synchronous Burst Address Advance

Synchronous Byte Write Enable

Write Enable

Clock Enable

Ground for Core

Not Connected

2M x 18

CE,

CE2,

CE2

Synchronous Chip Enable

DQa-DQd

DQPa-DQPd

MODE

DDQ

Output Enable

Synchronous Data Input/Output

Parity Data I/O

Burst Sequence Selection

+3.3V/2.5V Power Supply

Ground for output Buffer

Isolated Output Buffer Supply: +3.3V/2.5V

Snooze Enable

CLK

ADV

BWa-BWd

CKE

Vss

Integrated Silicon Solution, Inc. — www.issi.com

Rev. A

09/13/07

参数对比

与IS61NLP204818A-166B3相近的元器件有：IS61NLP102436A-166B3、IS61NLP204818A-166B3I、IS61NVP204818A-166B3、IS61NVP102436A-166B3、IS61NVP102436A-166B3I、IS61NVP204818A-166B3I、IS61NLP102436A-166B3I。描述及对比如下：

型号	IS61NLP204818A-166B3	IS61NLP102436A-166B3	IS61NLP204818A-166B3I	IS61NVP204818A-166B3	IS61NVP102436A-166B3	IS61NVP102436A-166B3I	IS61NVP204818A-166B3I	IS61NLP102436A-166B3I
描述	Standard SRAM, 2MX18, 3.5ns, CMOS, PBGA165, PLASTIC, BGA-165	Standard SRAM, 1MX36, 3.5ns, CMOS, PBGA165, PLASTIC, BGA-165	Standard SRAM, 2MX18, 3.5ns, CMOS, PBGA165, PLASTIC, BGA-165	Standard SRAM, 2MX18, 3.5ns, CMOS, PBGA165, PLASTIC, BGA-165	Standard SRAM, 1MX36, 3.5ns, CMOS, PBGA165, PLASTIC, BGA-165	Standard SRAM, 1MX36, 3.5ns, CMOS, PBGA165, PLASTIC, BGA-165	Standard SRAM, 2MX18, 3.5ns, CMOS, PBGA165, PLASTIC, BGA-165	Standard SRAM, 1MX36, 3.5ns, CMOS, PBGA165, PLASTIC, BGA-165
是否无铅	含铅	含铅	含铅	含铅	含铅	含铅	含铅	含铅
是否Rohs认证	不符合	不符合	不符合	不符合	不符合	不符合	不符合	不符合
零件包装代码	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA
包装说明	TBGA, BGA165,11X15,40	TBGA, BGA165,11X15,40	TBGA, BGA165,11X15,40	TBGA, BGA165,11X15,40	PLASTIC, BGA-165	PLASTIC, BGA-165	PLASTIC, BGA-165	PLASTIC, BGA-165
针数	165	165	165	165	165	165	165	165
Reach Compliance Code	not_compliant	not_compliant	not_compliant	not_compliant	unknown	unknown	unknown	unknown
ECCN代码	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
最长访问时间	3.5 ns	3.5 ns	3.5 ns	3.5 ns	3.5 ns	3.5 ns	3.5 ns	3.5 ns
其他特性	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)	166 MHz	166 MHz	166 MHz	166 MHz	166 MHz	166 MHz	166 MHz	166 MHz
I/O 类型	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 代码	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165
JESD-609代码	e0	e0	e0	e0	e0	e0	e0	e0
长度	15 mm	15 mm	15 mm	15 mm	15 mm	15 mm	15 mm	15 mm
内存密度	37748736 bit	37748736 bit	37748736 bit	37748736 bit	37748736 bit	37748736 bit	37748736 bit	37748736 bit
内存集成电路类型	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM
内存宽度	18	36	18	18	36	36	18	36
功能数量	1	1	1	1	1	1	1	1
端子数量	165	165	165	165	165	165	165	165
字数	2097152 words	1048576 words	2097152 words	2097152 words	1048576 words	1048576 words	2097152 words	1048576 words
字数代码	2000000	1000000	2000000	2000000	1000000	1000000	2000000	1000000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	70 °C	70 °C	85 °C	70 °C	70 °C	85 °C	85 °C	85 °C
组织	2MX18	1MX36	2MX18	2MX18	1MX36	1MX36	2MX18	1MX36
输出特性	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	TBGA	TBGA	TBGA	TBGA	TBGA	TBGA	TBGA	TBGA
封装等效代码	BGA165,11X15,40	BGA165,11X15,40	BGA165,11X15,40	BGA165,11X15,40	BGA165,11X15,40	BGA165,11X15,40	BGA165,11X15,40	BGA165,11X15,40
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	GRID ARRAY, THIN PROFILE	GRID ARRAY, THIN PROFILE	GRID ARRAY, THIN PROFILE	GRID ARRAY, THIN PROFILE	GRID ARRAY, THIN PROFILE	GRID ARRAY, THIN PROFILE	GRID ARRAY, THIN PROFILE	GRID ARRAY, THIN PROFILE
并行/串行	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
峰值回流温度（摄氏度）	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
电源	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5/3.3,3.3 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm
最大待机电流	0.075 A	0.075 A	0.075 A	0.075 A	0.075 A	0.075 A	0.075 A	0.075 A
最小待机电流	3.14 V	3.14 V	3.14 V	2.38 V	2.38 V	2.38 V	2.38 V	3.14 V
最大压摆率	0.4 mA	0.4 mA	0.45 mA	0.4 mA	0.4 mA	0.45 mA	0.45 mA	0.45 mA
最大供电电压 (Vsup)	3.465 V	3.465 V	3.465 V	2.625 V	2.625 V	2.625 V	2.625 V	3.465 V
最小供电电压 (Vsup)	3.135 V	3.135 V	3.135 V	2.375 V	2.375 V	2.375 V	2.375 V	3.135 V
标称供电电压 (Vsup)	3.3 V	3.3 V	3.3 V	2.5 V	2.5 V	2.5 V	2.5 V	3.3 V
表面贴装	YES	YES	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
端子面层	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
端子形式	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL
端子节距	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm
端子位置	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
处于峰值回流温度下的最长时间	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
宽度	13 mm	13 mm	13 mm	13 mm	13 mm	13 mm	13 mm	13 mm
厂商名称	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	-	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )