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IS61/64WV102416EDALL

IS61/64WV102416EDBLL

1Mx16 HIGH SPEED AYNCHRONOUS

CMOS STATIC RAM with ECC

KEY FEATURES



High-speed access time: 10ns, 12ns



Single power supply

– 1.65V-2.2V V

(IS61/64WV102416EDALL)

– 2.4V-3.6V V

(IS61/64WV102416EDBLL)

Error Detection and Correction with optional

ERR1/ERR2 output pin:

ERR1 pin indicates 1-bit error detection and

correction.



ERR2 pin indicates 2-bit error detection

DESCRIPTION

The

ISSI

IS61/64WV102416EDALL/EDBLL are high-speed,

low power, 16M bit static RAMs organized as 1M words by

16 bits. It is fabricated using

ISSI's

high-performance CMOS

technology and implemented ECC function to improve

reliability.

This highly reliable process coupled with innovative circuit

design techniques including ECC (SEC-DED: Single Error

Correcting-Double Error Detecting) yield high-performance

and highly reliable devices.

When CS# is HIGH (deselected), the device assumes a

standby mode at which the power dissipation can be

reduced down with CMOS input levels.

Easy memory

expansion is provided by using Chip Enable and Output

Enable inputs.

The active LOW Write Enable (WE#) controls both writing

and reading of the memory. A data byte allows Upper Byte

(UB#) and Lower Byte (LB#) access.

The IS61/64WV102416EDALL/EDBLL are packaged in the

JEDEC standard 48-pin mini BGA (6mm x 8mm), and 48-pin

TSOP (TYPE I)

NOVEMBER 2016



Three state outputs

Industrial and Automotive temperature support

Lead-free available



FUNCTIONAL BLOCK DIAGRAM

A0 – A19

DECODER

Memory

Lower IO ECC Upper IO ECC

Array Array Array Array

1Mx8 1Mx5 1Mx8

1Mx5

VDD

VSS

ERR1

ERR2

I/O0 – I/O7

I/O8 – I/O15

ECC

I/O

DATA

CIRCUIT

COLUMN I/O

Column I/O

CS#

OE#

WE#

UB#

LB#

CONTROL

CIRCUIT

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can

reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such

applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc.-

www.issi.com

Rev. A

11/20/2016

IS61/64WV102416EDALL

IS61/64WV102416EDBLL

PIN CONFIGURATIONS

48-Pin mini BGA(6mm x 8mm), A19 on G2

(Package Code : B)

48-Pin mini BGA (6mm x 8mm) , A19 on G2, ERR1/2

(Package Code : B2)

LB#

OE#

LB#

OE#

I/O8

UB#

CS#

I/O0

I/O8

UB#

CS#

I/O0

I/O9

I/O10

I/O1

I/O2

I/O9

I/O10

I/O1

I/O2

VSS

I/O11

A17

I/O3

VDD

VSS

I/O11

A17

I/O3

VDD

I/O12

A16

I/O4

VSS

VDD

I/O12

ERR1

A16

I/O4

VSS

I/O14

I/O13

A14

A15

I/O5

I/O6

I/O14

I/O13

A14

A15

I/O5

I/O6

I/O15

A19

A12

A13

WE#

I/O7

I/O15

A19

A12

A13

WE#

I/O7

A18

A10

A11

A18

A10

A11

ERR2

48-Pin mini BGA(6mm x 8mm), A19 on H6

(Package Code : B3)

48-Pin mini BGA (6mm x 8mm) , A19 on H6, ERR1/2

(Package Code : B4)

LB#

OE#

LB#

OE#

I/O8

UB#

CS#

I/O0

I/O8

UB#

CS#

I/O0

I/O9

I/O10

I/O1

I/O2

I/O9

I/O10

I/O1

I/O2

VSS

I/O11

A17

I/O3

VDD

VSS

I/O11

A17

I/O3

VDD

I/O12

A16

I/O4

VSS

VDD

I/O12

ERR1

A16

I/O4

VSS

I/O14

I/O13

A14

A15

I/O5

I/O6

I/O14

I/O13

A14

A15

I/O5

I/O6

I/O15

A12

A13

WE#

I/O7

I/O15

ERR2

A12

A13

WE#

I/O7

A18

A10

A11

A19

A18

A10

A11

A19

Integrated Silicon Solution, Inc.-

www.issi.com

Rev. A

11/20/2016

IS61/64WV102416EDALL

IS61/64WV102416EDBLL

48-Pin TSOP-I

48-Pin TSOP-I with ERR1/ERR2

OE#

ERR1

CS#

I/O0

I/O1

I/ O2

UB#

LB#

I/O15

CS#

I/O0

I/O1

I/O2

I/O3

VDD

UB#

LB#

I/O15

I/O14

I/O13

I/O12

VSS

I/O14

I/O13

I/O12

VSS

I/O3

VDD

VSS

I/O4

I/O5

I/O6

VDD

I/O11

VSS

I/O4

I/O5

I/O6

I/O7

VDD

I/O11

I/O10

I/O9

I/O8

I/O7

WE#

I/O8

A10

A11

WE#

ERR2

A19

A10

A11

A12

A13

A14

A19

A18

A17

A16

A15

A12

A13

A14

A18

A17

A16

A15

PIN DESCRIPTIONS

A0-A19

I/O0-I/O15

CS#

OE#

WE#

LB#

UB#

ERR1

ERR2

VSS

Address Inputs

Data Inputs/Outputs

Chip Enable Input

Output Enable Input

Write Enable Input

Lower-byte Control

(I/O0-I/O7)

Upper-byte Control

(I/O8-I/O15)

1-bit Error Detection and

Correction Signal

2-bit ERR Detection Signal

No Connection

Power

Ground

Integrated Silicon Solution, Inc.-

www.issi.com

Rev. A

11/20/2016

IS61/64WV102416EDALL

IS61/64WV102416EDBLL

FUNCTION DESCRIPTION

SRAM is one of random access memories. Each byte or word has an address and can be accessed randomly. SRAM

has three different modes supported. Each function is described below with Truth Table.

STANDBY MODE

Device enters standby mode when deselected (CS# HIGH). The input and output pins (I/O0-15) are placed in a high

impedance state. CMOS input in this mode will maximize saving power.

WRITE MODE

Write operation issues with Chip selected (CS#) and Write Enable (WE#) input LOW. The input and output pins (I/O0-

15) are in data input mode. Output buffers are closed during this time even if OE# is LOW. UB# and LB# enables a

byte write feature. By enabling LB# LOW, data from I/O pins (I/O0 through I/O7) are written into the location specified

on the address pins. And with UB# being LOW, data from I/O pins (I/O8 through I/O15) are written into the location.

READ MODE

Read operation issues with Chip selected (CS# LOW) and Write Enable (WE#) input HIGH. When OE# is LOW, output

buffer turns on to make data output. Any input to I/O pins during READ mode is not permitted. UB# and LB# enables a

byte read feature. By enabling LB# LOW, data from memory appears on I/O0-7. And with UB# being LOW, data from

memory appears on I/O8-15.

In the READ mode, output buffers can be turned off by pulling OE# HIGH. In this mode, internal device operates as

READ but I/Os are in a high impedance state. Since device is in READ mode, active current is used.

ERROR DETECTION AND ERROR CORRECTION



Independent ECC per each byte



detect and correct one bit error per byte or detect 2-bit error per byte

Optional ERR1 output signal indicates 1-bit error detection and correction

Optional ERR2 output signal indicates 2-bit error detection.

Controller can use either ERR1 or ERR2 to monitor ECC event. Unused pins (ERR1 or ERR2) can be left

floating.



Better reliability than parity code schemes which can only detect an error but not correct an error

Backward Compatible: Drop in replacement to current in industry standard devices (without ECC)

ERR1, ERR2 OUTPUT SIGNAL BEHAVIOR

ERR1

High-Z

ERR2

High-Z

DQ pin

Status

Remark

Valid Q No Error

Valid Q 1-Bit Error only

In-Valid Q 2-Bit Error only

1-bit error per byte detected and corrected

No 1-bit error. 2-bit error per byte detected (out of 2 bytes)

In-Valid Q 1-bit & 2-bit error 1-bit error detected and corrected at one byte, and 2-bit error detected at another byte.

Valid D Non-Read

Write operation or Output Disabled

Integrated Silicon Solution, Inc.-

www.issi.com

Rev. A

11/20/2016

IS61/64WV102416EDALL

IS61/64WV102416EDBLL

TRUTH TABLE

Mode

Not Selected

Output Disabled

Read

Write

High-Z

DOUT

High-Z

DOUT

DIN

High-Z

DIN

High-Z

DOUT

High-Z

DIN

ICC

CS#

WE#

OE#

LB#

UB#

I/O0-I/O7

High-Z

I/O8-I/O15

High-Z

ICC

VDD Current

SB1,

SB2

POWER UP INITIALIZATION

The device includes on-chip voltage sensor used to launch POWER-UP initialization process.

When VDD reaches stable level, the device requires 150us of tPU (Power-Up Time) to complete its self-initialization

process.

When initialization is complete, the device is ready for normal operation.

tPU

Stable VDD

150 us

VDD

Device Initialization

Device for Normal Operation

Integrated Silicon Solution, Inc.-

www.issi.com

Rev. A

11/20/2016

型号	IS61WV102416EDBLL-10B2LI	IS61WV102416EDBLL-10B2LI-TR	IS61WV102416EDBLL-10BLI-TR	IS61WV102416EDBLL-10T2LI	IS61WV102416EDBLL-10TLI	IS61WV102416EDBLL-10T2LI-TR	IS61WV102416EDBLL-10TLI-TR	IS61WV102416EDBLL-10BLI
描述	IC SRAM 16M PARALLEL 48MGA	Standard SRAM,	IC SRAM 16M PARALLEL 48MGA	IC SRAM 16M PARALLEL 48TSOP	IC SRAM 16M PARALLEL 48TSOP	IC SRAM 16M PARALLEL 48TSOP	Standard SRAM,	IC SRAM 16M PARALLEL 48MGA
技术	SRAM - 异步	CMOS	SRAM - 异步	SRAM - 异步	SRAM - 异步	SRAM - 异步	CMOS	SRAM - 异步
存储器类型	易失	-	易失	易失	易失	易失	-	易失
存储器格式	SRAM	-	SRAM	SRAM	SRAM	SRAM	-	SRAM
存储容量	16Mb （1M x 16）	-	16Mb （1M x 16）	16Mb （1M x 16）	16Mb （1M x 16）	16Mb （1M x 16）	-	16Mb （1M x 16）
写周期时间 - 字，页	10ns	-	10ns	10ns	10ns	10ns	-	10ns
访问时间	10ns	-	10ns	10ns	10ns	10ns	-	10ns
存储器接口	并联	-	并联	并联	并联	并联	-	并联
电压 - 电源	2.4 V ~ 3.6 V	-	2.4 V ~ 3.6 V	2.4 V ~ 3.6 V	2.4 V ~ 3.6 V	2.4 V ~ 3.6 V	-	2.4 V ~ 3.6 V
工作温度	-40°C ~ 85°C（TA）	-	-40°C ~ 85°C（TA）	-40°C ~ 85°C（TA）	-40°C ~ 85°C（TA）	-40°C ~ 85°C（TA）	-	-40°C ~ 85°C（TA）