IS62/65WV102416DALL
IS62/65WV102416DBLL
JANUARY 2015
1Mx16 LOW VOLTAGE,
ULTRA LOW POWER & LOW POWER CMOS STATIC RAM
KEY FEATURES
High-speed access time: 45ns, 55ns.
CMOS low power operation
–
25 µA (typical) CMOS standby
CMOS for optimum speed and power and TTL
compatible interface levels
Single power supply
–
1.65V~1.98V V
DD
(IS62/65WV102416DALL)
–
2.2V~3.6V V
DD
(IS62/65WV102416DBLL)
Fully static operation: no clock or refresh
required
Industrial and Automotive temperature support
DESCRIPTION
The
ISSI
IS62/65WV102416DALL,
IS62/65WV102416DBLL are ULTRA LOW POWER
CMOS 16Mbit static RAMs organized as 1M words
by 16 bits. It is fabricated using
ISSI's
high-
performance CMOS technology. This highly reliable
process coupled with innovative circuit design
techniques, yields high-performance and low power
consumption devices. The IS62WV102416DALL/
DBLL and IS65WV102416DALL/DBLL are
packaged in 48-Pin TSOP (TYPE I).
BLOCK DIAGRAM
A0-19
A20
DECODER
MEMORY ARRAY
(1024KX16)
(2048KX8)
COLUMN I/O
I/O0-7
I/O8-14
I/O15
IO15
CONTROL CIRCUIT
,
CS2
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.-
www.issi.com
Rev. A
12/12/2014
1
IS62/65WV102416DALL
IS62/65WV102416DBLL
48-PIN TSOP-I
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
CS2
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
Vss
I/O15/A20
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
Vcc
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
Vss
A0
A18
A17
A7
A6
A5
A4
A3
A2
A1
PIN DESCRIPTIONS
A0-A19
I/O0-I/O14
I/O15/A20
, CS2
Address Inputs
Data Inputs/Outputs, I/O8 to I/O14 pins are not used in x8 Mode.
I/O15, when used in a x16 Mode. A20 when used in a x8 Mode,
Chip Enable Input
Output Enable Input
Write Enable Input
Lower-byte Control (I/O0-I/O7). This pin is not used in x8 Mode.
Upper-byte Control (I/O8-I/O15). This pin is not used in x8 Mode.
pin must be tied to either V
DD
to use the device as a 1024Kx16
SRAM or GND to use as 2048Kx8 SRAM. In x8 mode, Pin 45
becomes A20, while
,
and I/O8 to I/O14 pins are not used.
No Connection
Power
Ground
NC
VDD
Vss
*For x8/x16 switchable configuration BGA option, please contact sram@issi.com
Integrated Silicon Solution, Inc.-
www.issi.com
Rev. A
12/12/2014
2
IS62/65WV102416DALL
IS62/65WV102416DBLL
FUNCTION DESCRIPTION
SRAM is one of random access memories. Each byte or word has an address and can be accessed randomly. SRAM
has three different modes supported. Each function is described below with Truth Table.
STANDBY MODE
Device enters standby mode when deselected (
HIGH or CS2 LOW or both
and
are HIGH). The input and
output pins (I/O0-15) are placed in a high impedance state. The current consumption in this mode will be either ISB1 or
ISB2 depending on the input level. CMOS input in this mode will maximize saving power.
WRITE MODE
Write operation issues with Chip selected (
LOW and CS2 HIGH) and Write Enable (
) input LOW. The input and
output pins(I/O0-15) are in data input mode. Output buffers are closed during this time even if
is LOW.
and
enables a byte write feature. By enabling
LOW, data from I/O pins (I/O0 through I/O7) are written into the location
specified on the address pins. And with
being LOW, data from I/O pins (I/O8 through I/O15) are written into the
location.
READ MODE
Read operation issues with Chip selected (
LOW and CS2 HIGH) and Write Enable (
) input HIGH. When
is
LOW, output buffer turns on to make data output. Any input to I/O pins during READ mode is not permitted.
and
enables a byte read feature. By enabling
LOW, data from memory appears on I/O0-7. And with
being LOW,
data from memory appears on I/O8-15.
In the READ mode, output buffers can be turned off by pulling
HIGH. In this mode, internal device operates as
READ but I/Os are in a high impedance state. Since device is in READ mode, active current is used.
TRUTH TABLE
Mode
Not Selected
Output Disabled
Read
H
X
X
L
L
L
L
L
L
L
L
CS2
X
L
X
H
H
H
H
H
H
H
H
X
X
X
H
H
H
H
H
L
L
L
X
X
X
H
H
L
L
L
X
X
X
X
X
H
L
X
L
H
L
L
H
L
X
X
H
X
L
H
L
L
H
L
L
I/O0-I/O7
High-Z
High-Z
High-Z
High-Z
High-Z
DOUT
High-Z
DOUT
DIN
High-Z
DIN
I/O8-I/O15
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DOUT
DOUT
High-Z
DIN
DIN
VDD Current
ISB1,ISB2
ICC
ICC
Write
ICC
Integrated Silicon Solution, Inc.-
www.issi.com
Rev. A
12/12/2014
3
IS62/65WV102416DALL
IS62/65WV102416DBLL
ABSOLUTE MAXIMUM RATINGS AND OPERATING RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Vter m
tBIAS
V
DD
tStg
I
OUT
Notes:
1.
Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Parameter
Terminal Voltage with Respect to GND
Temperature Under Bias
V
DD
Related to GND
Storage Temperature
DC Output Current (LOW)
Value
–0.2 to +3.9(V
DD
+0.3V)
–55 to +125
–0.2 to +3.9(V
DD
+0.3V)
–65 to +150
20
Unit
V
C
V
C
mA
OPERATING RANGE
(1)
Range
Commercial
Industrial
Automotive
Commercial
Industrial
Automotive
Device Marking
IS62WV102416DALL
IS62WV102416DALL
IS65WV102416DALL
IS62WV102416DBLL
IS62WV102416DBLL
IS65WV102416DBLL
Ambient Temperature
0C to +70C
-40C to +85C
-40C to +125C
0C to +70C
-40C to +85C
-40C to +125C
V
DD
(min)
1.65V
1.65V
1.65V
2.2V
2.2V
2.2V
V
DD
(typ)
1.8V
1.8V
1.8V
3.3V
3.3V
3.3V
V
DD
(max)
1.98V
1.98V
1.98V
3.6V
3.6V
3.6V
Note:
1. Full device AC operation assumes a 100 µs ramp time from 0 to Vcc(min) and 200 µs wait time after Vcc stabilization.
PIN CAPACITANCE
(1)
Parameter
Input capacitance
DQ capacitance (IO0–IO15)
Symbol
C
IN
C
I/O
Test Condition
T
A
= 25°C, f = 1 MHz, V
DD
= V
DD
(typ)
Max
10
10
Units
pF
pF
Note:
1. These parameters are guaranteed by design and tested by a sample basis only.
THERMAL CHARACTERISTICS
(1)
Parameter
Thermal resistance from junction to ambient (airflow = 1m/s)
Thermal resistance from junction to case
Note:
1. These parameters are guaranteed by design and tested by a sample basis only.
Symbol
R
θJA
R
θJC
Rating
43.8
7.7
Units
°C/W
°C/W
Integrated Silicon Solution, Inc.-
www.issi.com
Rev. A
12/12/2014
4
IS62/65WV102416DALL
IS62/65WV102416DBLL
ELECTRICAL CHARACTERISTICS
IS62(5)WV102416DALL DC ELECTRICAL CHARACTERISTICS-I (OVER THE OPERATING RANGE)
Symbol
V
OH
V
OL
V
IH(1)
V
IL(1)
I
LI
I
LO
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage
Output Leakage
Test Conditions
I
OH
= -0.1 mA
I
OL
= 0.1 mA
Min.
1.4
—
1.4
–0.2
–1
–1
Max.
—
0.2
V
DD
+ 0.2
0.4
1
1
Unit
V
V
V
V
µA
µA
GND < V
IN
< V
DD
GND < V
IN
< V
DD
, Output Disabled
Notes:
1. V
ILL
(min) = -1.0V AC (pulse width < 10ns). Not 100% tested.
V
IHH
(max) = VDD + 1.0V AC (pulse width < 10ns). Not 100% tested.
IS62(5)WV102416DBLL DC ELECTRICAL CHARACTERISTICS-I (OVER THE OPERATING RANGE)
Symbol
V
OH
V
OL
V
IH(1)
V
IL(1)
I
LI
I
LO
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage
Output Leakage
Test Conditions
2.2 ≤ V
DD
< 2.7, I
OH
= -0.1 mA
2.7 ≤ V
DD
≤ 3.6, I
OH
= -1.0 mA
2.2 ≤ V
DD
< 2.7, I
OL
= 0.1 mA
2.7 ≤ V
DD
≤ 3.6, I
OL
= 2.1 mA
2.2 ≤ V
DD
< 2.7
2.7 ≤ V
DD
≤ 3.6
2.2 ≤ V
DD
< 2.7
2.7 ≤ V
DD
≤ 3.6
GND < V
IN
< V
DD
GND < V
IN
< V
DD
, Output Disabled
Min.
2.0
2.4
—
—
1.8
2.2
–0.3
–0.3
–1
–1
Max.
—
—
0.4
0.4
V
DD
+ 0.3
V
DD
+ 0.3
0.6
0.8
1
1
Unit
V
V
V
V
V
V
V
V
µA
µA
Notes:
1. V
ILL
(min) = -2.0V AC (pulse width < 10ns). Not 100% tested.
V
IHH
(max) = VDD + 2.0V AC (pulse width < 10ns). Not 100% tested.
Integrated Silicon Solution, Inc.-
www.issi.com
Rev. A
12/12/2014
5
