liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. C
11/03/2017
1
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
BLOCK DIAGRAM
MODE
CLK
/CKE
/ADV
/ADSC
/ADSP
A0-x
x18: x=20
x36: x=19
BINARY
COUNTER
/CE
/CLR
20/21
D
ADDRESS
REGISTER
/CE
CLK
/GW
/BWE
/BW(a-x)
x18:x=b,
x32,x36:x=d
/CE
CE2
/CE2
D
ENABLE
REGISTERS
CLK
ZZ
Q
CLK
OUTPUT
REGISTER
DQ(a-x)
x18:x=b,
x32,x36:x=d
D
Q
DQ(a-d)
BYTE WRITE
REGISTERS
CLK
Q
18/19
1Mx36;
2Mx18
Memory Array
Q1
Q0
A0
A0`
A1
A1`
INPUT
REGISTER
Power
Down
CLK
D
Q
ENABLE DELAY
REGISTERS
CLK
/OE
2
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
165-PIN BgA
165-Ball, 13x15 mm BGA
119-PIN BgA
119-Ball, 14x22 mm BGA
BOTTOM VIEW
BOTTOM VIEW
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. C
11/03/2017
3
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
119 BGA PACKAGE PIN CONFIGURATION-
1M
x
36 (TOP VIEW)
1
A
B
C
D
E
F
g
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQc
DQc
V
DDQ
DQc
DQc
V
DDQ
DQd
DQd
V
DDQ
DQd
DQd
NC
NC
V
DDQ
2
A
A
A
DQPc
DQc
DQc
DQc
DQc
V
DD
DQd
DQd
DQd
DQd
DQPd
A
NC
TMS
3
A
A
A
Vss
Vss
Vss
BWc
Vss
NC
Vss
BWd
Vss
Vss
Vss
MODE
A
TDI
4
ADSP
ADSC
V
DD
NC
CE
OE
ADV
GW
V
DD
CLK
NC
BWE
A
1
*
A
0
*
V
DD
A
TCK
5
A
A
A
Vss
Vss
Vss
BWb
Vss
NC
Vss
BWa
Vss
Vss
Vss
NC
A
TDO
6
A
A
A
DQPb
DQb
DQb
DQb
DQb
V
DD
DQa
DQa
DQa
DQa
DQPa
A
A
NC
7
V
DDQ
NC
NC
DQb
DQb
V
DDQ
DQb
DQb
V
DDQ
DQa
DQa
V
DDQ
DQa
DQa
NC
ZZ
V
DDQ
Note:
* A
0
and A
1
are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
ADSP
ADSC
GW
CLK
CE, CE2
BWa-BWd
BWE
Pin Name
Synchronous Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address
Advance
Synchronous Address Status Processor
Synchronous Address Status Controller
Synchronous Global Write Enable
Synchronous Clock
Synchronous Chip Select
Synchronous Byte Write Controls
Synchronous Byte Write Enable
Symbol
OE
ZZ
MODE
TCK, TDO
TMS, TDI
NC
DQa-DQd
DQPa-DQPd
V
dd
V
ddq
Vss
No Connect
Synchronous Data Inputs/Outputs
Synchronous Parity Data
Inputs/Outputs
Power Supply
I/O Power Supply
Ground
Pin Name
Asynchronous Output Enable
Asynchronous Power Sleep Mode
Burst Sequence Selection
JTAG Pins
4
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. C
11/03/2017
IS61(64)LPS102436B/IS61(64)VPS/VVPS102436B
IS61(64)LPS204818B/IS61(64)VPS/VVPS204818B
119 BGA PACKAGE PIN CONFIGURATION
2M
x
18 (TOP VIEW)
1
A
B
C
D
E
F
g
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQb
NC
V
DDQ
NC
DQb
V
DDQ
NC
DQb
V
DDQ
DQb
NC
NC
NC
V
DDQ
2
A
A
A
NC
DQb
NC
DQb
NC
V
DD
DQb
NC
DQb
NC
DQPb
A
A
TMS
3
A
A
A
Vss
Vss
Vss
BWb
Vss
NC
Vss
Vss
Vss
Vss
Vss
MODE
A
TDI
4
ADSP
ADSC
V
DD
NC
CE
OE
ADV
GW
V
DD
CLK
NC
BWE
A
1
*
A
0
*
V
DD
A
TCK
5
A
A
A
Vss
Vss
Vss
Vss
Vss
NC
Vss
BWa
Vss
Vss
Vss
NC
A
TDO
6
A
A
A
DQPa
NC
DQa
NC
DQa
V
DD
NC
DQa
NC
DQa
NC
A
A
NC
7
V
DDQ
NC
NC
NC
DQa
V
DDQ
DQa
NC
V
DDQ
DQa
NC
V
DDQ
NC
DQa
NC
ZZ
V
DDQ
Note:
* A
0
and A
1
are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
ADSP
ADSC
GW
CLK
CE, CE2
BWa-BWb
BWE
Pin Name
Synchronous Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address
Advance
Synchronous Address Status Processor
Synchronous Address Status Controller
Synchronous Global Write Enable
Synchronous Clock
Synchronous Chip Select
Synchronous Byte Write Controls
Synchronous Byte Write Enable
Symbol
OE
ZZ
MODE
TCK, TDO
TMS, TDI
NC
DQa-DQb
DQPa-DQPb
V
dd
V
ddq
Vss
No Connect
Synchronous Data Inputs/Outputs
Synchronous Parity Data
Inputs/Outputs
Power Supply
I/O Power Supply
Ground
Pin Name
Asynchronous Output Enable
Asynchronous Power Sleep Mode
Burst Sequence Selection
JTAG Pins
Integrated Silicon Solution, Inc. — www.issi.com —
