IS61WV5128ALL/ALS
IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
512K x 8 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM
AUGUST 2009
FEATURES
HIGH SPEED: (IS61/64WV5128ALL/BLL)
• High-speed access time: 8, 10, 20 ns
• Low Active Power: 85 mW (typical)
• Low stand-by power: 7 mW (typical)
CMOS standby
LOW POWER: (IS61/64WV5128ALS/BLS)
• High-speed access time: 25, 35 ns
• Low Active Power: 35 mW (typical)
• Low stand-by power: 0.6 mW (typical)
CMOS standby
• Single power supply
— V
dd
1.65V to 2.2V (IS61WV5128Axx)
— V
dd
2.4V to 3.6V (IS61/64WV5128Bxx)
• Fully static operation: no clock or refresh
required
• Three state outputs
• Industrial and Automotive temperature support
• Lead-free available
DESCRIPTION
The
ISSI
IS61WV5128Axx and IS61/64WV5128Bxx
are very high-speed, low power, 524,288-word by
8-bit CMOS static RAMs. The IS61WV5128Axx and
IS61/64WV5128Bxx are fabricated using
ISSI
's high-
performance CMOS technology. This highly reliable pro-
cess coupled with innovative circuit design techniques,
yields higher performance and low power consumption
devices.
When
CE
is HIGH (deselected), the device assumes
a standby mode at which the power dissipation can be
reduced down with CMOS input levels.
The IS61WV5128Axx and IS61/64WV5128Bxx operate
from a single power supply.
The IS61WV5128ALL and IS61/64WV5128BLL are avail-
able in 36-pin 400-mil SOJ, 36-pin mini BGA, and 44-pin
TSOP (Type II) packages.
The IS61WV5128ALS and IS61/64WV5128BLS are
available in 32-pinTSOP (Type I), 32-pin sTSOP (Type I),
32-pin SOP and 32-pin TSOP (Type II) packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A18
DECODER
512K X 8
MEMORY ARRAY
V
DD
GND
I/O
DATA
CIRCUIT
I/O0-I/O7
COLUMN I/O
CE
OE
WE
CONTROL
CIRCUIT
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
1
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
PIN CONFIGURATION (HIGH SPEED) (61/64WV5128ALL/BLL)
36 mini BGA
44-Pin TSOP (Type II)
1
2
3
4
5
6
A
B
C
D
E
F
G
H
A0
I/O4
I/O5
GND
V
DD
I/O6
I/O7
A9
A1
A2
NC
WE
NC
A3
A4
A5
A6
A7
A8
I/O0
I/O1
V
DD
GND
A18
OE
A10
CE
A11
A17
A16
A12
A15
A13
I/O2
I/O3
A14
NC
NC
A0
A1
A2
A3
A4
CE
I/O0
I/O1
V
DD
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
A18
A17
A16
A15
OE
I/O7
I/O6
GND
V
DD
I/O5
I/O4
A14
A13
A12
A11
A10
NC
NC
NC
PIN DESCRIPTIONS
A0-A18
CE
OE
WE
I/O0-I/O7
V
dd
GND
NC
Address Inputs
Chip Enable Input
Output Enable Input
Write Enable Input
Bidirectional Ports
Power
Ground
No Connection
36-Pin SOJ
A0
A1
A2
A3
A4
CE
I/O0
I/O1
V
DD
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A18
A17
A16
A15
OE
I/O7
I/O6
GND
V
DD
I/O5
I/O4
A14
A13
A12
A11
A10
NC
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
PIN CONFIGURATION (LOW POWER) (61/64WV5128ALS/BLS)
32-pin TSOP (TYPE I), (Package Code T)
32-pin sTSOP (TYPE I) (Package Code H)
32-pin SOP
32-pin TSOP (TYPE II)
(Package Code T2)
A11
A9
A8
A13
WE
A18
A15
V
DD
A17
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
DD
A15
A18
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
PIN DESCRIPTIONS
A0-A18
CE
OE
WE
I/O0-I/O7
V
dd
GND
Address Inputs
Chip Enable 1 Input
Output Enable Input
Write Enable Input
Input/Output
Power
Ground
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
3
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
V
DD
= 3.3V + 5%
Symbol
V
oh
V
ol
V
Ih
V
Il
I
lI
I
lo
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
(1)
Input Leakage
Output Leakage
Test Conditions
V
dd
=
Min.,
I
oh
=
–4.0 mA
V
dd
=
Min.,
I
ol
=
8.0 mA
Min.
2.4
—
2
–0.3
–1
–1
Max.
—
0.4
V
dd
+ 0.3
0.8
1
1
Unit
V
V
V
V
µA
µA
GND
≤
V
In
≤
V
dd
GND
≤
V
out
≤
V
dd
,
Outputs Disabled
Note:
1.
V
Il
(min.) = –0.3V
DC; V
Il
(min.) = –2.0V AC (pulse width <10 ns). Not 100% tested.
V
Ih
(max.) = V
dd
+
0.3V dC; V
Ih
(max.) = V
dd
+
2.0V AC
(pulse width <10 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
V
DD
= 2.4V-3.6V
Symbol
V
oh
V
ol
V
Ih
V
Il
I
lI
I
lo
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
(1)
Input Leakage
Output Leakage
Test Conditions
V
dd
=
Min.,
I
oh
=
–1.0 mA
V
dd
=
Min.,
I
ol
=
1.0 mA
Min.
1.8
—
2.0
–0.3
–1
–1
Max.
—
0.4
V
dd
+ 0.3
0.8
1
1
Unit
V
V
V
V
µA
µA
GND
≤
V
In
≤
V
dd
GND
≤
V
out
≤
V
dd
,
Outputs Disabled
Note:
1.
V
Il
(min.) = –0.3V
DC; V
Il
(min.) = –2.0V AC (pulse width <10 ns). Not 100% tested.
V
Ih
(max.) = V
dd
+
0.3V dC; V
Ih
(max.) = V
dd
+
2.0V AC
(pulse width <10 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
V
DD
= 1.65V-2.2V
Symbol
V
oh
V
ol
V
Ih
V
Il
(1)
I
lI
I
lo
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage
Output Leakage
Test Conditions
V
dd
= Min, I
oh
=
-0.1 mA
V
dd
= Min, I
ol
=
0.1 mA
Min.
1.4
—
1.4
–0.2
–1
–1
Max.
—
0.2
V
dd
+ 0.2
0.4
1
1
Unit
V
V
V
V
µA
µA
GND
≤
V
In
≤
V
dd
GND
≤
V
out
≤
V
dd
,
Outputs Disabled
Note:
1.
V
Il
(min.) = –0.3V
DC; V
Il
(min.) = –2.0V AC (pulse width <10 ns). Not 100% tested.
V
Ih
(max.) = V
dd
+
0.3V dC; V
Ih
(max.) = V
dd
+
2.0V AC
(pulse width <10 ns). Not 100% tested.
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
TRUTH TABLE
Mode
WE
Not Selected
X
(Power-down)
Output Disabled H
Read
Write
H
L
CE
H
L
L
L
OE
X
H
L
X
I/O Operation V
DD
Current
High-Z
I
sb
1
, I
sb
2
High-Z
d
out
d
In
I
CC
I
CC
I
CC
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
terM
V
dd
t
stg
P
t
Parameter
Terminal Voltage with Respect to GND
V
dd
Relates to GND
Storage Temperature
Power Dissipation
Value
–0.5 to V
dd
+ 0.5
–0.3 to 4.0
–65 to +150
1.0
Unit
V
V
°C
W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
CAPACITANCE
(1,2)
Symbol
C
In
C
I/o
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
V
In
= 0V
V
out
= 0V
Max.
6
8
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25°C,
f = 1 MHz, V
dd
= 3.3V.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
5
FPGA/CPLD
