DATASHEET
ISL33001, ISL33002, ISL33003
I2C Bus Buffer with Rise Time Accelerators and Hot Swap Capability
The ISL33001, ISL33002, ISL33003 are 2-Channel Bus Buffers
that provide the buffering necessary to extend the bus
capacitance beyond the 400pF maximum specified by the I
2
C
specification. In addition, the ISL33001, ISL33002, ISL33003
feature rise time accelerator circuitry to reduce power
consumption from passive bus pull-up resistors and improve
data-rate performance. All devices also include hot swap circuitry
to prevent corruption of the data and clock lines when I
2
C devices
are plugged into a live backplane, and the ISL33002 and
ISL33003 add level translation for mixed supply voltage
applications. The ISL33001, ISL33002, ISL33003 operate at
supply voltages from +2.3V to +5.5V at a temperature range of
-40°C to +85°C.
FN7560
Rev 6.00
July 11, 2014
Features
• 2 Channel I
2
C compatible bi-directional buffer
• +2.3VDC to +5.5VDC supply range
• >400kHz operation
• Bus capacitance buffering
• Rise time accelerators
• Hot swapping capability
• ±6kV Class 3 HBM ESD protection on all pins
• ±12kV HBM ESD protection on SDA/SCL pins
• Enable pin (ISL33001 and ISL33003)
• Logic level translation (ISL33002 and ISL33003)
• READY logic pin (ISL33001)
• Accelerator disable pin (ISL33002)
• Pb-free (RoHS Compliant) 8 Ld SOIC (ISL33001 only),
8 Ld TDFN (3mmx3mm) and 8 Ld MSOP packages
• Low quiescent current . . . . . . . . . . . . . . . . . . . . . . . 2.1mA typ
• Low shutdown current . . . . . . . . . . . . . . . . . . . . . . . . 0.5µA typ
Summary of Features
PART
NUMBER
ISL33001
ISL33002
ISL33003
LEVEL
TRANSLATION
No
Yes
Yes
ENABLE READY
PIN
PIN
Yes
No
Yes
Yes
No
No
ACCELERATOR
DISABLE
No
Yes
No
Related Literature
•
AN1543,
“ISL33001MSOPEVAL1Z, ISL33002MSOPEVAL1Z,
ISL33003MSOPEVAL1Z Evaluation Board User’s Manual”
•
AN1637,
“Level Shifting Between 1.8V and 3.3V Using I
2
C
Buffers”
Applications
• I
2
C bus extender and capacitance buffering
• Server racks for telecom, datacom, and computer servers
• Desktop computers
• Hot-swap board insertion and bus isolation
V
CC1
+3.3V
+5.0V
V
CC2
100kHz I
2
C BUS WITH 2.7kΩ PULL-UP RESISTOR
AND 400pF BUS CAPACITANCE
WITHOUT BUFFER
µC
BACK
PLANE
SDA
I
2
C
DEVICE
A
I
2
C
VOLTAGE (1V/DIV)
SDA
SCL
EN
ISL33003
SCL
WITH BUFFER
DEVICE
B
GND
TIME (2µs/DIV)
FIGURE 1. TYPICAL OPERATING CIRCUIT
FIGURE 2. BUS ACCELERATOR PERFORMANCE
FN7560 Rev 6.00
July 11, 2014
Page 1 of 18
ISL33001, ISL33002, ISL33003
Ordering Information
PART NUMBER
(Notes
1, 2, 3)
ISL33001IRTZ
ISL33001IRT2Z
ISL33001IBZ
ISL33001IUZ
ISL33002IRTZ
ISL33002IRT2Z
ISL33002IUZ
ISL33003IRTZ
ISL33003IRT2Z
ISL33003IUZ
ISL33001MSOPEVAL1Z
ISL33002MSOPEVAL1Z
ISL33003MSOPEVAL1Z
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for
ISL33001, ISL33002, ISL33003.
For more information on MSL please
see techbrief
TB363.
3001
01R2
33001 IBZ
33001
3002
02R2
33002
3003
03R2
33003
ISL33001 Evaluation Board
ISL33002 Evaluation Board
ISL33003 Evaluation Board
PART
MARKING
TEMP. RANGE
(°C)
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
PACKAGE
(Pb-free)
8 Ld TDFN (0.65mm Pitch)
8 Ld TDFN (0.5mm Pitch)
8 Ld SOIC
8 Ld MSOP
8 Ld TDFN (0.65mm Pitch)
8 Ld TDFN (0.5mm Pitch)
8 Ld MSOP
8 Ld TDFN (0.65mm Pitch)
8 Ld TDFN (0.5mm Pitch)
8 Ld MSOP
PKG.
DWG. #
L8.3x3A
L8.3x3H
M8.15
M8.118
L8.3x3A
L8.3x3H
M8.118
L8.3x3A
L8.3x3H
M8.118
Pin Configurations
ISL33001
(8 LD TDFN)
TOP VIEW
EN
SCL_OUT
SCL_IN
GND
ISL33001
(8 LD SOIC, MSOP)
TOP VIEW
V
CC1
SDA_OUT
SDA_IN
READY
EN 1
SCL_OUT 2
SCL_IN 3
GND 4
8
7
6
5
V
CC1
SDA_OUT
SDA_IN
READY
1
2
3
4
8
7
6
5
PAD
ISL33002
(8 LD TDFN)
TOP VIEW
V
CC2
1
SCL_OUT 2
SCL_IN 3
GND 4
V
CC1
SDA_OUT
SDA_IN
ACC
V
CC2
SCL_OUT
SCL_IN
GND
ISL33002
(8 LD MSOP)
TOP VIEW
V
CC1
SDA_OUT
SDA_IN
ACC
8
7
6
5
1
2
3
4
8
7
6
5
PAD
FN7560 Rev 6.00
July 11, 2014
Page 2 of 18
ISL33001, ISL33002, ISL33003
Pin Configurations
ISL33003
(8 LD TDFN)
TOP VIEW
(Continued)
ISL33003
(8 LD MSOP)
TOP VIEW
V
CC2
1
SCL_OUT 2
PAD
SCL_IN 3
GND 4
8
7
6
5
V
CC1
SDA_OUT
SDA_IN
EN
V
CC2
SCL_OUT
SCL_IN
GND
1
2
3
4
8
7
6
5
V
CC1
SDA_OUT
SDA_IN
EN
Pin Descriptions
PIN
PIN NAME NUMBER
V
CC1
V
CC2
8
1
FUNCTION
V
CC1
power supply, +2.3V to +5.5V. Decouple V
CC1
to ground with a high frequency
0.01µF to 0.1µF capacitor.
V
CC2
power supply, +2.3V to +5.5V. Decouple V
CC2
to ground with a high frequency ISL33002 (8 LD TDFN, 8 LD MSOP)
0.01µF to 0.1µF capacitor. In level shifting applications, SDA_OUT and SCL_OUT logic ISL33003 (8 LD TDFN, 8 LD MSOP)
thresholds are referenced to V
CC2
supply levels. Connect pull-up resistors on these
pins to V
CC2
.
Device Ground Pin
Buffer Enable Pin. Logic “0” disables the device. Logic “1” enables the device. Logic ISL33001 (8 LD TDFN, 8 LD SOIC, MSOP)
threshold referenced to V
CC1
.
ISL33003 (8 LD TDFN, 8 LD MSOP)
ISL33001 only
Buffer active ‘Ready’ open drain logic output. When buffer is active, READY is high
impedance. When buffer is inactive, READY is low impedance to ground. Connect to
10kΩ pull-up resistor to V
CC1
.
Rise Time Accelerator Enable Pin. Logic “0” disables the accelerator. Logic “1”
enables the accelerator. Logic threshold referenced to V
CC1
.
Data I/O Pins
ISL33002 only
NOTES
GND
EN
4
1
5
READY
5
ACC
SDA_IN
SDA_OUT
SCL_IN
SCL_OUT
PAD
5
6
7
3
2
Clock I/O Pins
Thermal pad should be connected to ground or floated.
Thermal Pad; TDFN only
FN7560 Rev 6.00
July 11, 2014
Page 3 of 18
ISL33001, ISL33002, ISL33003
Absolute Maximum Ratings
(All voltages referenced to GND)
V
CC1
, V
CC2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
SDA_IN, SCL_IN, SDA_OUT, SCL_OUT, READY. . . . . . . . . . . . . -0.3V to +7V
EN, ACC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +(V
CC1
+ 0.3)V
Maximum Sink Current (SDA and SCL Pins) . . . . . . . . . . . . . . . . . . . . 20mA
Maximum Sink Current (READY pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7mA
Latch-Up Tested per JESD78, Level 2, Class A . . . . . . . . . . . . . . . . . . 85°C
ESD Ratings. . . . . . . . . . . . . . . . . . . . . . See
“ESD PROTECTION” on page 5
Thermal Information
Thermal Resistance
JA
(°C/W)
JC
(°C/W)
47
4
8 Ld TDFN Package (Notes
5, 6)
. . . . . . . . . .
(0.50mm Pitch)
8 Ld TDFN Package (Notes
5, 6)
. . . . . . . . . .
48
6
(0.65mm Pitch)
8 Ld MSOP Package (Notes
4, 7)
. . . . . . . . .
151
50
8 Ld SOIC Package (Notes
4, 7)
. . . . . . . . . .
120
56
Maximum Storage Temperature Range . . . . . . . . . . . . . -65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see
TB493
Operating Conditions
Temperature Range, T
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
V
CC1
and V
CC2
Supply Voltage Range . . . . . . . . . . . . . . . . . +2.3V to +5.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379
for details.
5.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief
TB379.
6. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
7. For
JC
, the “case temp” location is taken at the package top center.
Electrical Specifications
PARAMETER
POWER SUPPLIES
V
CC1
Supply Range
V
CC2
Supply Range
Supply Current from V
CC1
V
CC1
V
CC2
I
CC1
V
EN
= V
CC1
, V
CC1
= +2.3V to +5.5V, V
CC2
= +2.3V to +5.5V, unless otherwise noted (Note
8).
Boldface limits apply
over the operating temperature range, -40°C to +85°C.
SYMBOL
CONDITIONS
TEMP
(°C)
Full
ISL33002 and ISL33003
V
CC1
= 5.5V; ISL33001 only (Note
11)
V
CC1
= V
CC2
= 5.5V; ISL33002 and ISL33003
(Note
11)
Supply Current from V
CC2
V
CC1
Shut-down Supply
Current
V
CC2
Shut-down Supply
Current
START-UP CIRCUITRY
Precharge Circuitry
Voltage
Enable High Threshold
Voltage
Enable Low Threshold
Voltage
Enable Pin Input Current
Enable Delay, On-Off
Enable Delay, Off-On
Bus Idle Time
Ready Pin OFF State
Leakage Current
Ready Delay, On-Off
V
PRE
V
EN_H
V
EN_L
I
EN
t
EN-HL
t
EN-LH
t
IDLE
I
OFF
t
READY-HL
Enable from 0V to V
CC1;
ISL33001 and
ISL33003
ISL33001 and ISL33003 (Note
10)
ISL33001 and ISL33003 (Figure
3)
(Figure
4, Note 12)
ISL33001 only
ISL33001 only (Note
10)
SDA and SCL pins floating
Full
+25
+25
Full
+25
+25
Full
+25
+25
0.8
-
MIN
(Note
9)
2.3
2.3
-
-
-
-
-
-
TYP
-
-
2.1
2.0
0.22
0.5
0.05
0.06
MAX
(Note
9)
5.5
5.5
4.0
3.0
0.6
-
-
-
UNITS
V
V
mA
mA
mA
µA
µA
µA
Full
Full
Full
Full
Full
Full
Full
I
CC2
I
SHDN1
V
CC2
= V
CC1
= 5.5V; ISL33002 and ISL33003
(Note
11)
V
CC1
= 5.5V, V
EN
= GND; ISL33001 only
V
CC1
= V
CC2
= 5.5V, V
EN
= GND; ISL33003 only
(Note
13)
I
SHDN2
V
CC1
= V
CC2
= 5.5V, V
EN
= GND, ISL33003 only
(Note
13)
1
0.5*V
CC
0.5*V
CC
0.1
10
86
83
0.1
10
1.2
0.7*V
CC
-
1
-
-
150
1
-
V
V
V
µA
ns
µs
µs
µA
ns
0.3*V
CC
-1
-
-
50
-1
-
FN7560 Rev 6.00
July 11, 2014
Page 4 of 18
ISL33001, ISL33002, ISL33003
Electrical Specifications
PARAMETER
Ready Delay, Off-On
Ready Output Low Voltage
RISE-TIME ACCELERATORS
Transient Accelerator
Current
Accelerator Pin Enable
Threshold
Accelerator Pin Disable
Threshold
Accelerator Pin Input
Current
Accelerator Delay, On-Off
ESD PROTECTION
SDA, SCL I/O Pins
All Pins
INPUT-OUTPUT CONNECTIONS
Input Low Threshold
Input-Output Offset
Voltage
Output Low Voltage
V
IL
V
OS
V
EN
= V
CC1
, V
CC1
= +2.3V to +5.5V, V
CC2
= +2.3V to +5.5V, unless otherwise noted (Note
8).
Boldface limits apply
over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
t
READY-LH
V
OL_READY
I
TRAN_ACC
V
ACC_EN
V
ACC_DIS
I
ACC
t
PDOFF
CONDITIONS
ISL33001 only (Note
10)
V
CC1
= +2.5V, I
PULLUP
= 3mA; ISL33001 only
V
CC1
= 2.7V, V
CC2
= 2.7V ; (ACC = 0.7*V
CC1
for
ISL33002 only) (Figure
8)
ISL33002 only
ISL33002 only
ISL33002 only
ISL33002 only (Note
10)
Human Body Model, SDA and SCL pins to ground
only (JESD22-A114)
Machine Model (JESD22-A115)
Class 3 HBM ESD (JESD22-A114)
V
CC1
= V
CC2
, 10kto V
CC1
on SDA and SCL pins
V
CC1
= 3.3V, 10kto V
CC1
on SDA and SCL pins,
V
INPUT
= 0.2V; V
CC2
= 3.3V, ISL33002 and
ISL33003 (Figure
5)
V
CC1
= 2.7V, V
INPUT
= 0V, I
SINK
= 3mA on
SDA/SCL pins; V
CC2
= 2.7V, ISL33002 and
ISL33003 (Figure
6)
(Figure
25)
SDA and SCL pins = V
CC1
= 5.5V;
V
CC2
= 5.5V, ISL33002 and ISL33003
C
LOAD
= 100pF, 2.7kto V
CC1
on SDA and SCL
pins, V
CC1
= 3.3V; V
CC2
= 3.3V, ISL33002 and
ISL33003 (Figure
7)
C
LOAD
= 100pF, 2.7kto V
CC1
on SDA and SCL
pins, V
CC1
= 3.3V; V
CC2
= 3.3V, ISL33002 and
ISL33003 (Figure
7)
TEMP
(°C)
+25
Full
+25
+25
+25
+25
+25
+25
+25
+25
+25
Full
-
0
MIN
(Note
9)
-
-
-
-
0.3*V
CC1
-1
-
-
-
TYP
10
-
5
0.5*V
CC1
0.5*V
CC1
0.1
10
±12
±400
±6
-
50
MAX
(Note
9)
-
0.4
-
0.7*V
CC1
-
UNITS
ns
V
mA
V
V
µA
ns
kV
V
kV
V
mV
1
-
-
-
-
0.3*V
CC1
150
V
OL
Full
-
-
0.4
V
Buffer SDA and SCL Pins
Input Capacitance
Input Leakage Current
TIMING CHARACTERISTICS
SCL/SDA Propagation
Delay High-to-Low
SCL/SDA Propagation
Delay Low-to-High
NOTES:
C
IN
I
LEAK
+25
Full
-
-5
10
0.1
-
5
pF
µA
t
PHL
+25
0
27
100
ns
t
PLH
+25
0
2
26
ns
8. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
10. Typical value determined by design simulations. Parameter not tested.
11. Buffer is in the connected state.
12. ISL33002 and ISL33003 limits established by characterization. Not production tested.
13. If the V
CC1
and V
CC2
voltages diverge, then the shut down I
CC
increases on the higher voltage supply.
FN7560 Rev 6.00
July 11, 2014
Page 5 of 18
