6-Channel LED Driver with Ultra Low Dimming
Capability
ISL97672B
The ISL97672B is an integrated 6-channel power LED driver for
LCD backlight applications. ISL97672B is capable of driving
LEDs with input from 4.5V to 26.5V and maximum output up to
45V.
The ISL97672B employs an adaptive boost switching
architecture that allows Direct PWM dimming with dimming
duty cycle as low as 0.007% at 200Hz or 0.8% at 20kHz. PWM
Dimming frequency can be as high as 30kHz.
The ISL97672B employs the dynamic headroom control that
monitors the highest LED forward voltage string for output
regulation to minimize headroom voltage and power loss in a
typical multi-string operation. Typical current matching between
channels is ±0.7%.
The ISL97672B incorporates extensive protection functions
that flag whenever a fault occurs. The protections include
string-open and short-circuit detections, OVP, OTP, and an
optional output short-circuit protection with external fault
disconnect switch
The ISL97672B is offered in a compact 20 Ld QFN 3x4
package and can operate in ambient temperatures of -40°C to
+85°C.
Features
• 6 x 50mA channels
• 4.5V to 26.5V input
• 45V output max
• Adaptive boost switching architecture
• Direct PWM dimming with dimming linearity of
0.007%~100% at 200Hz or 0.8%~100% <20kHz
• Adjustable 200kHz to 1.4MHz switching frequency
• Dynamic headroom control
• Fault protections with latched flag indication
- String open/short circuit
- OVP
- OTP
- Optional output short-circuit fault protection switch
• Current matching ±0.7%
• 20 Ld 3x4 QFN package
Applications
• Notebook displays LED backlighting
• LCD monitor LED backlighting
• Multi-function printer scanning light source
V
IN
= 4.5V~26.5V
Q1 OPTIONAL
V
OUT
= 45V*, 6 x 50mA
ISL97672B
1 FAULT
2 VIN
4 VDC
6 /FLAG
18 COMP
CH1 11
3 EN
5 PWM
17 RSET
8 FSW
9 AGND
CH2 12
CH3 13
CH4 14
CH5 15
* V
IN
> 12V
I
LED
(mA)
CH0 10
LX 20
OVP 16
PGND 19
1.2
1.0
0.8
0.6
0.4
0.2
0.0
I
LED
= 20mA
F
PWM
= 20kHz
0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2
PWM DIMMING DUTY CYCLE (%)
FIGURE 1. TYPICAL APPLICATION DIAGRAM
FIGURE 2. DIMMING LINEARITY AT 20kHz
November 22, 2013
FN7995.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
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Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL97672B
Block Diagram
V
IN
: 4.5V~26.5V
FAULT
10µH/1.5A
LX
O/P SHORT
OVP
FAULT
FLAG
OSC & RAMP
COMP
/FLAG
FAULT
FLAG
COMP
GM
AMP
8-BIT
DAC
DYNAMIC
HEADROOM
CONTROL
HIGHEST VF
STRING
DETECT
OPEN CKT, SHORT CKT
DETECTION
CH1
CH2
CH3
+
-
REF
GEN
1
2
3
4
5
REF_
OVP
REF_
VSC
CH4
CH5
CH6
* V
IN
= 12V
OVP
4.7µF/50V
45V*, 6x50mA
VIN
INTERNAL
BIAS
EN
REG
VDC
SUM = 0
I
MAX
ILIMIT
LOGIC
FET
DRIVERS
PGND
+
-
ISET
6
+
-
PWM
DIMMING CONTROLLER
ISL97672B
TEMP
SENSOR
FIGURE 3. ISL97672B BLOCK DIAGRAM
Ordering Information
PART
NUMBER
(Notes 1, 2, 3)
ISL97672BIRZ
ISL97672BIRZ-EVAL
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to Tech Brief
TB347
for
details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is
RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information
page for
ISL97672B.
For more information on MSL, please see Tech
Brief
TB363.
PART
MARKING
672B
PACKAGE
(Pb-Free)
20 Ld 3x4 QFN
PKG.
DWG. #
L20.3x4
Pin Configuration
ISL97672B
(20 LD 3X4 QFN)
TOP VIEW
COMP
18
PGND
RSET
17
16
15
14
13
12
11
7
NC
8
FSW
9
AGND
10
CH0
OVP
CH5
CH4
CH3
CH2
CH1
LX
20
FAULT
VIN
EN
VDC
PWM
/FLAG
1
2
3
4
5
6
Evaluation Board
19
2
FN7995.1
November 22, 2013
ISL97672B
Pin Descriptions
(I = Input, O = Output, S = Supply)
PIN NAME
FAULT
VIN
EN
VDC
PWM
/FLAG
NC
FSW
AGND
CH0, CH1
CH2, CH3
CH4, CH5
OVP
RSET
COMP
PGND
LX
PIN #
1
2
3
4
5
6
7
8
9
10, 11,
12, 13,
14, 15
16
17
18
19
20
TYPE
O
S
I
S
I
O
I
I
S
I
DESCRIPTION
A pull-down current output for external P-channel fault disconnect switch.
Input supply voltage for IC. Connect a 0.1µF decoupling capacitor close to this pin.
IC enable pin. Pull high to enable the IC. If EN is low for longer than 30µs, the IC will be disabled.
Internal 5V regulator. Connect a 1µF decoupling capacitor on VDC.
PWM input pin for direct PWM dimming control.
/FLAG is latched low under any fault condition and resets after input power is recycled or part is re-enabled. This
pin is an open drain that needs pull-up.
No Connect.
Boost switching frequency set pin. Connect a resistor between this pin and ground to set up desired boost switching
frequency. See “Switching Frequency” on page 9 for resistance calculation.
Analog Ground for precision circuits.
Current source and channel monitoring input for Channel 0, 1, 2 3, 4, 5.
I
I
O
S
O
Overvoltage protection input. See “OVP and V
OUT
” on page 10.
LED DC current set pin. Connect a resistor between this pin and ground to set up maximum LED DC current. See
“Maximum DC Current Setting” for resistance calculation.
Boost compensation pin. Connect a RC compensation network between this pin and GND to optimize boost stability
and transient response.
Power ground.
Boost converter switching node
3
FN7995.1
November 22, 2013
ISL97672B
Absolute Maximum Ratings
(T
A
= +25°C)
VIN, EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 28V
FAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIN - 8.5V to VIN + 0.3V
VDC, COMP, RSET, PWM, OVP, FSW . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.5V
CH0 - CH5, LX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 45V
PGND, AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
NOTE: Voltage ratings are with respect to AGND pin.
ESD Rating
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . 3kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 300V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1kV
Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA
Thermal Information
Thermal Resistance (Typical)
θ
JA
(°C/W)
θ
JC
(°C/W)
20 Ld QFN Package (Notes 4, 5, 7) . . . . . .
40
2.5
Thermal Characterization (Typical)
PSI
JT
(°C/W)
20 Ld QFN Package (Note 6) . . . . . . . . . . . . . . . . . . . . .
1
Maximum Continuous Junction Temperature . . . . . . . . . . . . . . . . .+125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4.
θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief
TB379.
5. For
θ
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
6. PSI
JT
is the junction-to-top thermal resistance. If the package top temperature can be measured, with this rating then the die junction temperature
can be estimated more accurately than the
θ
JA
and
θ
JC
thermal resistance ratings.
7. Refer to JESD51-7 high effective thermal conductivity board layout for proper via and plane designs.
All specifications are tested at T
A
= +25°C, V
IN
= 12V, EN = 5V, R
SET
= 20.1kΩ, unless otherwise noted. Boldface
limits apply over the operating junction temperature range, -40°C to +85°C.
PARAMETER
DESCRIPTION
CONDITION
MIN
(Note 8)
TYP
MAX
(Note 8)
UNIT
Electrical Specifications
GENERAL
V
IN
(Note 10)
IVIN
IVIN_STBY
V
OUT
VIN Supply Voltage
VIN Current
VIN Shutdown Current
Output Voltage
T
C
= <+60°C
T
A
= +25°C
EN = 5V
T
A
= +25°C
4.5V < V
IN
≤
26V,
F
SW
= 600kHz
8.55V < V
IN
≤
26V,
F
SW
= 1.2MHz
4.5V < V
IN
≤
8.55V,
F
SW
= 1.2MHz
V
UVLO
V
UVLO_HYS
Undervoltage Lock-out Threshold
Undervoltage Lock-out Hysteresis
2.1
200
4.5
5
5
45
45
V
IN
/0.19
2.6
26.5
V
mA
µA
V
V
V
V
mV
ENABLE AND PWM GENERATOR
V
IL
V
IH
FPWM
t
ON
Guaranteed Range for PWM Input Low Voltage
Guaranteed Range for PWM Input High Voltage
PWM Input Frequency Range
Minimum On Time
1.5
200
250
0.8
VDD
30,000
350
V
V
Hz
ns
4
FN7995.1
November 22, 2013
ISL97672B
All specifications are tested at T
A
= +25°C, V
IN
= 12V, EN = 5V, R
SET
= 20.1kΩ, unless otherwise noted. Boldface
limits apply over the operating junction temperature range, -40°C to +85°C.
PARAMETER
DESCRIPTION
CONDITION
MIN
(Note 8)
TYP
MAX
(Note 8)
UNIT
Electrical Specifications
REGULATOR
VDC
IVDC_STBY
VLDO
EN
Low
EN
Hi
t
ENLow
LDO Output Voltage
Standby Current
VDC LDO Droop Voltage
Guaranteed Range for EN Input Low Voltage
Guaranteed Range for EN Input High Voltage
EN Low Time Before Shut-down
1.8
30
V
IN
> 6V
EN = 0V
V
IN
> 5.5V, 20mA
20
4.55
4.8
5
5
200
0.5
V
µA
mV
V
V
us
BOOST
SW
ILimit
r
DS(ON)
SS
Eff_peak
Boost FET Current Limit
Internal Boost Switch ON-Resistance
Boost Soft-start Time
Peak Efficiency
T
A
= +25°C
100% LED Duty Cycle
V
IN
= 12V, 72 LEDs, 20mA
each, L = 10µH with DCR
101mΩ, T
A
= +25°C
V
IN
= 12V, 60 LEDs, 20mA
each, L = 10µH with DCR
101mΩ, T
A
= +25°C
ΔI
OUT
/ΔV
IN
D
max
Line Regulation
Boost Maximum Duty Cycle
F
SW
= 600kHz
F
SW
= 1.2MHz
D
min
Boost Minimum Duty Cycle
F
SW
= 600kHz
F
SW
= 1.2MHz
f
S
f
S
I
LX_leakage
Minimum Switching Frequency
Maximum Switching Frequency
LX Leakage Current
R
FSW
= 200kΩ
R
FSW
= 33kΩ
LX = 45V, EN = 0
175
1.312
200
1.50
90
81
9.5
17
235
1.69
10
1.5
2.0
235
7
92.9
2.7
300
A
mΩ
ms
%
90.8
%
0.1
%
%
%
%
%
kHz
MHz
µA
CURRENT SOURCES
I
MATCH
I
ACC
V
headroom20
V
headroom33
V
RSET
I
LEDmax
Channel-to-Channel Current Matching
Current Accuracy
Dominant Channel Current Source Headroom
at IIN Pin measured with I
LED
=20mA
Dominant Channel Current Source Headroom
at IIN Pin measured with I
LED
=33mA
Voltage at RSET Pin
Maximum LED Current per Channel
I
LED
= 20mA
T
A
= +25°C
I
LED
= 33mA
T
A
= +25°C
R
SET
= 20.5kΩ
V
IN
= 12V, V
OUT
= 45V,
F
SW
= 1.2MHz, T
A
= +25°C
560
(Note 9)
1.2
R
SET
=20.5kΩ
(I
OUT
= 20mA)
-1.5
500
(Note 9)
710
1.22
50
860
(Note 9)
1.24
±0.7
±1.0
+1.5
%
%
mV
mV
V
mA
FAULT DETECTION
VSC
Temp_shtdwn
Temp_Hyst
VOVPlo
Channel Short Circuit Threshold
Over- Temperature Shutdown Threshold
Over- Temperature Shutdown Hysteresis
Overvoltage Limit on OVP Pin
1.199
PWM Dimming = 100%
7.5
8.2
150
23
1.24
V
°C
°C
V
5
FN7995.1
November 22, 2013
