ispGAL™22V10 Device Datasheet
June 2010
All Devices Discontinued!
Product Change Notifications (PCNs) have been issued to discontinue all devices in this
data sheet.
The original datasheet pages have not been modified and do not reflect those changes.
Please refer to the table below for reference PCN and current product status.
Product Line
ispGAL22V10C
Ordering Part Number
ispGAL22V10C-7LJ
ispGAL22V10C-7LJN
ispGAL22V10C-10LJ
ispGAL22V10C-10LJN
ispGAL22V10C-15LJ
ispGAL22V10C-15LJN
ispGAL22V10C-15LJI
ispGAL22V10C-7LK
ispGAL22V10C-10LK
ispGAL22V10C-15LK
ispGAL22V10C-15LKI
Product Status
Reference PCN
PCN#06-07
Discontinued
PCN#09-10
5555 N.E. Moore Ct.
Hillsboro, Oregon 97124-6421 Phone (503) 268-8000
Internet: http://www.latticesemi.com
FAX (503) 268-8347
ree
Lead-F ge
P a c k a ns
Optio le!
b
Availa
ispGAL22V10
In-System Programmable E
2
CMOS PLD
Generic Array Logic™
Features
• IN-SYSTEM PROGRAMMABLE™ (5-V ONLY)
— 4-Wire Serial Programming Interface
— Minimum 10,000 Program/Erase Cycles
— Built-in Pull-Down on SDI Pin Eliminates Discrete
Resistor on Board (ispGAL22V10C Only)
• HIGH PERFORMANCE E CMOS TECHNOLOGY
— 7.5 ns Maximum Propagation Delay
— Fmax = 111 MHz
— 5 ns Maximum from Clock Input to Data Output
— UltraMOS
®
Advanced CMOS Technology
2
®
Functional Block Diagram
I/CLK
RESET
8
OLMC
I/O/Q
I
10
I
12
OLMC
I/O/Q
A
D LL
IS
C DE
O
VI
N
TI CE
N
S
U
ED
I
OLMC
I/O/Q
PROGRAMMABLE
AND-ARRAY
(132X44)
I
14
• ACTIVE PULL-UPS ON ALL LOGIC INPUT AND I/O PINS
• COMPATIBLE WITH STANDARD 22V10 DEVICES
— Fully Function/Fuse-Map/Parametric Compatible
with Bipolar and CMOS 22V10 Devices
• E CELL TECHNOLOGY
— In-System Programmable Logic
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
2
OLMC
I/O/Q
I
16
OLMC
I/O/Q
I
16
OLMC
I/O/Q
I
14
OLMC
I
I/O/Q
• TEN OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
• APPLICATIONS INCLUDE:
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Software-Driven Hardware Configuration
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
• LEAD-FREE PACKAGE OPTIONS
12
I
OLMC
I/O/Q
I
10
OLMC
I/O/Q
I
8
SDO
SDI
MODE
SCLK
OLMC
I/O/Q
PROGRAMMING
LOGIC
PRESET
Description
Pin Configuration
PLCC
SCLK
Vcc
The ispGAL22V10, at 7.5ns maximum propagation delay time,
combines a high performance CMOS process with Electrically Eras-
able (E
2
) floating gate technology to provide the industry's first in-
system programmable 22V10 device. E
2
technology offers high
speed (<100ms) erase times, providing the ability to reprogram or
reconfigure the device quickly and efficiently.
The generic architecture provides maximum design flexibility by al-
lowing the Output Logic Macrocell (OLMC) to be configured by the
user. The ispGAL22V10 is fully function/fuse map/parametric com-
patible with standard bipolar and CMOS 22V10 devices. The stan-
dard PLCC package provides the same functional pinout as the
standard 22V10 PLCC package with No-Connect pins being used
for the ISP interface signals.
SSOP
I/CLK
4
2
28
26
I/O/Q
I/O/Q
I
I
I
I
I
5
25
I/O/Q
I/O/Q
I/O/Q
SDO
7
ispGAL22V10
Top View
23
MODE
I
9
21
I/O/Q
I/O/Q
I/O/Q
I
I
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lat-
tice Semiconductor delivers 100% field programmability and func-
tionality of all GAL products. In addition, 10,000 erase/write cycles
and data retention in excess of 20 years are specified.
11 12
14
16
18 19
SCLK
I/CLK
I
I
I
I
I
MODE
I
I
I
I
I
GND
1
28
7
ispGAL
22V10
22
Top View
14
15
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
SDO
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
SDI
I
I
GND
SDI
I
Copyright © 2004 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
I/O/Q
I/O/Q
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
August 2004
isp22v10_04
1
Specifications
ispGAL22V10
Ordering Information
Conventional Packaging
Commercial Grade Specifications
Tpd (ns)
7.5
10
15
Tsu (ns)
6.5
7
10
Tco (ns)
5
7
8
Icc (mA)
140
140
140
Ordering #
ispGAL22V10C-7LJ
1
ispGAL22V10C-7LK
ispGAL22V10C-10LJ
ispGAL22V10C-10LK
ispGAL22V10C-15LJ
ispGAL22V10C-15LK
Package
28-Lead PLCC
28-Lead SSOP
28-Lead PLCC
28-Lead SSOP
28-Lead PLCC
28-Lead SSOP
Industrial Grade Specifications
Tpd (ns)
15
Tsu (ns)
10
Tco (ns)
8
Lead-Free Packaging
Commercial Grade Specifications
Tpd (ns)
7.5
10
15
Tsu (ns)
6.5
7
10
Tco (ns)
5
7
1. Discontinued per PCN #06-07. Contact Rochester Electronics for available inventory.
ispGAL22V10C
Device Name
Speed (ns)
A
D LL
IS
C DE
O
VI
N
TI CE
N
S
U
ED
Icc (mA)
165
Ordering #
Package
ispGAL22V10C-15LJI
28-Lead PLCC
ispGAL22V10C-15LKI
28-Lead SSOP
Icc (mA)
140
140
Ordering #
Package
ispGAL22V10C-7LJN
1
Lead-Free 28-Lead PLCC
ispGAL22V10C-10LJN
Lead-Free 28-Lead PLCC
8
140
ispGAL22V10C-15LJN
Lead-Free 28-Lead PLCC
Part Number Description
XXXXXXXX _ XX
X XX X
Grade
Blank = Commercial
I = Industrial
L = Low Power
Power
Package
J = PLCC
JN = Lead-Free PLCC
K = SSOP
2
Specifications
ispGAL22V10
Output Logic Macrocell (OLMC)
The ispGAL22V10 has a variable number of product terms per
OLMC. Of the ten available OLMCs, two OLMCs have access to
eight product terms (pins 17 and 27), two have ten product terms
(pins 18 and 26), two have twelve product terms (pins 19 and 25),
two have fourteen product terms (pins 20 and 24), and two OLMCs
have sixteen product terms (pins 21 and 23). In addition to the
product terms available for logic, each OLMC has an additional
product-term dedicated to output enable control.
The output polarity of each OLMC can be individually programmed
to be true or inverting, in either combinatorial or registered mode.
This allows each output to be individually configured as either active
high or active low.
The ispGAL22V10 has a product term for Asynchronous Reset (AR)
and a product term for Synchronous Preset (SP). These two prod-
uct terms are common to all registered OLMCs. The Asynchronous
Reset sets all registers to zero any time this dedicated product term
is asserted. The Synchronous Preset sets all registers to a logic
one on the rising edge of the next clock pulse after this product term
is asserted.
NOTE: The AR and SP product terms will force the Q output of the
flip-flop into the same state regardless of the polarity of the output.
Therefore, a reset operation, which sets the register output to a zero,
may result in either a high or low at the output pin, depending on
the pin polarity chosen.
Each of the Macrocells of the ispGAL22V10 has two primary func-
tional modes: registered, and combinatorial I/O. The modes and
the output polarity are set by two bits (SO and S1), which are nor-
mally controlled by the logic compiler. Each of these two primary
modes, and the bit settings required to enable them, are described
below and on the following page.
REGISTERED
In registered mode the output pin associated with an individual
OLMC is driven by the Q output of that OLMC’s D-type flip-flop.
Logic polarity of the output signal at the pin may be selected by
specifying that the output buffer drive either true (active high) or
inverted (active low). Output tri-state control is available as an in-
dividual product-term for each OLMC, and can therefore be defined
by a logic equation. The D flip-flop’s /Q output is fed back into the
AND array, with both the true and complement of the feedback
available as inputs to the AND array.
A
D LL
IS
C DE
O
VI
N
TI CE
N
S
U
ED
A R
D
Q
4 TO 1
MUX
CLK
Q
SP
2 TO 1
MUX
ispGAL22V10 OUTPUT LOGIC MACROCELL (OLMC)
Output Logic Macrocell Configurations
NOTE: In registered mode, the feedback is from the /Q output of
the register, and not from the pin; therefore, a pin defined as reg-
istered is an output only, and cannot be used for dynamic
I/O, as can the combinatorial pins.
COMBINATORIAL I/O
In combinatorial mode the pin associated with an individual OLMC
is driven by the output of the sum term gate. Logic polarity of the
output signal at the pin may be selected by specifying that the output
buffer drive either true (active high) or inverted (active low). Out-
put tri-state control is available as an individual product-term for
each output, and may be individually set by the compiler as either
“on” (dedicated output), “off” (dedicated input), or “product-term
driven” (dynamic I/O). Feedback into the AND array is from the pin
side of the output enable buffer. Both polarities (true and inverted)
of the pin are fed back into the AND array.
3
Specifications
ispGAL22V10
Registered Mode
AR
AR
D
Q
A
D LL
IS
C DE
O
VI
N
TI CE
N
S
U
ED
CLK
Q
CLK
Q
D
Q
SP
SP
ACTIVE LOW
ACTIVE HIGH
S
0
= 0
S
1
= 0
S
0
= 1
S
1
= 0
Combinatorial Mode
ACTIVE LOW
ACTIVE HIGH
S
0
= 0
S
1
= 1
S
0
= 1
S
1
= 1
4
