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JLC1562B
I
2
C Bus I/O Expander
The JLC1562B facilitates easy I
2
C Bus expandibility. Multiple
devices (up to 8 on the same I
2
C Bus) are easily added as each device
has its own selectable 3−bit address. The JLC1562B provides an 8−bit
bidirectional input/output port and 6−bit resolution Digital to Analog
Converter. The voltage on pins P0−P4 is compared with a controllable
threshold voltage and the results are readable through the I
2
C Bus.
I
2
C Bus interface pins SDA, SCL and A0−A2 are; Serial Data,
Serial Clock and Device Address respectively. External interface pins
are P0−P7 and VDAC; I/O Port and D/A output.
Features
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MARKING
DIAGRAMS
PDIP−16
N SUFFIX
CASE 648
1
16
JLC1562BN
AWLYYWWG
1
16
SOEIAJ−16
F SUFFIX
CASE 966
1
1
A
WL, L
YY, Y
WW, W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
JLC1562B
ALYWG
•
•
•
•
•
•
•
•
•
Low Power Dissipation
I
2
C−Bus Format (2−Wire Type; SDA, SCL) Data Transfer
6−bit DAC
Bus Address Selectable (3−bit)
Address Input Pins are Pulled Up to V
DD
with Internal Resistor
I/O Pins are Open Drain Outputs
5 Comparators at Inputs
Inputs Protected from External Bus Currents in Power Down Mode
Pb−Free Packages are Available*
A0
A1
A2
P0
P1
P2
P3
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
SDA
SCL
VDAC
P7
P6
P5
P4
ORDERING INFORMATION
Device
JLC1562BN
JLC1562BNG
JLC1562BF
JLC1562BFG
JLC1562BFEL
JLC1562BFELG
Package
PDIP−16
PDIP−16
(Pb−Free)
SOEIAJ−16
SOEIAJ−16
(Pb−Free)
SOEIAJ−16
SOEIAJ−16
(Pb−Free)
Shipping
†
25 Units/Tube
25 Units/Tube
50 Units/Rail
50 Units/Rail
2000/Tape & Reel
2000/Tape & Reel
Figure 1. Pin Assignment
PIN LIST
A0−A2
P0−P4
P5−P7
SCL
SDA
VDAC
Chip Address Input
Comparator Input / Open Drain Output
Comparator Input / Open Drain Output
Serial Clock Input
I
2
C Data Output
DAC Output
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2005
1
November, 2005 − Rev. 5
Publication Order Number:
JLC1562B/D
JLC1562B
Power−On
Reset
SDA
8 Bit
I2C Bus Controller
6 Bit
Latch
6−Bit
DAC
Latch
SCL
V
DD
Write Buffer
P7
P6
P5
P4
P3
P2
P1
P0
VDAC
1/2 V
CC
Comp.
A
(C5−C7)
Latch
5 Bit
5 Bit
3 Bit
Comp.
B
(C0−C4)
Comparator “B”
V
ref
Write Data (2)
V
ref
Selector
Bit D6 of Write Data (2)
D6
1
0
V
ref
Value
V
ref
= VDAC
V
+
40 V
ref
80 DD
Write Data (2)
D5
1
D4
1
D3
1
D2
1
•
•
•
•
1LSB
+
1 V
80 DD
0
0
0
0
0
0
0
0
0
0
1
0
D1
1
D0
1
V
ref
64 V
80 DD
•
•
•
•
2 V
80 DD
1 V
80 DD
2
A0
A1
A2
NOTE: Internal Power On Reset sets P0 ~ P7 low, sets VDAC to 1/80 V
DD
and selects 1/2 V
DD
for Comparator “B” threshold.
Figure 2. Block Diagram
Pin 1
VDAC
V
DD
16 X R
65
R
64
R
63
R
40
R
39
R
2
R
1
GND
6:64 De−MUX (1 of 64 Decoder)
Bits D0 − D5 of Write Data (2)
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Shift Register (PISO) (SIPO)
JLC1562B
ÎÎÎÎ
Î
Î
Î
Î
ÎÎÎÎ
Î
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
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Î
Î
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Î
Î
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Î
Î
Î
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Î
Î
Î
Î
Î
Î
Î
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Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
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Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS (Referenced to GND)
Symbol
V
dd
V
in
Parameter
Value
Unit
V
V
V
DC Supply Voltage
DC Input Voltage
–0.5 to +7.0
–0.5 to V
dd
+0.5
–0.5 to V
dd
+0.5
25
75
V
out
I
DC Output Voltage
DC Input/Output Current (per Pin)
mA
mA
°C
°C
I
DD
DC Supply Current (V
DD
and GND Pins)
Storage Temperature Range
T
stg
T
L
–65 to +150
300
Lead Temperature, 1 mm from Case for 10 Seconds
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
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Î
Î
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
V
dd
Parameter
Min
4.2
0.0
Max
6.0
Unit
V
V
DC Supply Voltage
DC Input Voltage
V
in
, V
out
T
A
V
dd
Operating Temperature
–40
+85
°C
RECOMMENDED OPERATING CONDITIONS
DC CHARACTERISTICS
(Referenced to V
ss
)
Symbol
V
IH
V
IL
V
OL
I
in
I
oz
C
in
C
out
C
i/o
V
ICR
I
CC
Maximum Input Voltage, “H”
Maximum Input Voltage, “L”
Guaranteed Limit
Parameter
Min
0.7 V
dd
−
−
−
−
−
−
−
0
−
Max
−
0.3 V
dd
0.3
±
1.0
±
5.0
10
15
15
V
dd
−1.5
5.0
Unit
V
V
V
mA
mA
pF
pF
pF
V
mA
Maximum Output Voltage, “L” (I
out
= 4mA)
Maximum Input Leakage Current (V
in
= V
dd
or V
ss
, SCL pin only)
Maximum Output Hi−Z Leakage Current (Output = High Impedance; V
out
= V
dd
)
Maximum Input Capacitance (Input Pin)
Maximum Output Capacitance (Output Pin)
Maximum I/O Capacitance (I/O Pin)
Comparator Common Mode Input Voltage Range
Maximum Quiescent Supply Current (per Package)
COMPARATOR AC CHARACTERISTICS
Guaranteed Limit
Symbol
t
PD
Parameter
Maximum Propagation Delay
Test Conditions
V
ref
= 1.5 V, 10mV overdrive
V
ref
= 1.5 V, 100mV overdrive
Min
−
−
Typ
1.0
0.2
Max
−
−
Unit
mS
mS
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3
JLC1562B
DA COMPARATOR CHARACTERISTICS
Guaranteed Limit
Symbol
DNL
e
FS
e
ZC
DAC Referential NON−Linearity
DAC Full Scale Error
DAC Zero Scale Error
Parameter
Min
Typ
±1/4
LSB
±1
LSB
±1
LSB
Max
Unit
TIMING CHARACTERISTICS
Guaranteed Limit
Symbol
f
CL
t
BUF
t
HD:STA
t
LOW
t
HIGH
t
HD:DAT
t
SU:DAT
t
R
t
F
t
SU:STO
SCL CLOCK Frequency
BUS Free Time (Between “STOP” and “START”)
HOLD Time for “START”
HOLD Time at SCL CLOCK LOW
HOLD Time at SCL CLOCK HI
DATA HOLD Time
DATA SETUP Time
Rise Time (SDA and SCL)
Fall Time (SDA and SCL)
SETUP Time for “STOP”
Parameter
Min
0
4.7
4.0
4.7
4.0
0
250
−
−
4.0
Max
100
−
−
−
−
−
−
1000
300
−
Unit
kHz
ms
ms
ms
ms
ms
ns
ns
ns
ms
SDA
t
BUF
SCL
t
LOW
t
R
t
F
t
HD:STA
t
HD:DAT
t
HIGH
t
SU:DAT
t
SU:STO
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4
