TS81102G0
8/10 bit – 2 GSPS 1:8/1:4 DEMUX
DESCRIPTION
The DEMUX is designed to fit with TCS high speed ADC
TS8387 and TS8388B and further G’core ADC 2 and
4GSPS family.
This DEMUX allows users to process the high speed out-
put data stream down to processor speed. It uses the very
high speed bipolar technology (25 GHz NPN cutt–off fre-
quency) B6HF from SIEMENS.
MAIN FEATURES
H
Programmable Demux ratio :
. 1:4 : Data Rate max=1GSPS,
P
D (8b/10b)
< 3.7 / 4.1 W
(ECL 50
W
output)
. 1:8 : Data Rate max=2GSPS,
P
D (8b/10b)
< 5.1/ 5.9 W
(ECL 50
W
output)
. 1:16 with 1 TS8388 and 2 DEMUX.
H
Parallel output mode.
H
8 /10 bit, with nap mode for the 2 unused bit.
H
ECL Differential input data.
H
DataReady or DataReady/2 input clock.
H
Input clock sampling delay adjust.
H
Single ended output data :
. Adjustable common mode and swing
. Logic threshold reference output
. (ECL, PECL, TTL).
H
Asynchronous reset.
H
Synchronous reset
(to be confirmed).
H
ADC + DEMUX multi–channel applications :
. Stand–alone delay adjust cell for ADCs sampling
instant alignment
H
Differential data ready output.
H
Built–in self test (BIST).
H
Dual supply V
EE
= –5 V, Vcc = +5 V,
H
Radiation tolerance oriented design (more than
100Krad (Si) expected).
SCREENING
H
TCS standard screening level.
H
Mil–PRF–38535, QML level Q for hermetic package only
(TBC)
H
Space screening level according to ESA/SCC 9000
(TBC)
H
Temperature range : 0°C < Tc < +70
°C
–40°C <Tc < +85°C
1/13
– Evaluation board for TBGA 240 package
– Hermetic package :
CI–CGA 360 on request only
– Package : TBGA 240
Tape Ball Grid Array (cavity down)
May 1999
TS81102G0
Table of Contents
1. BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2. PACKAGE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2. TBGA 240 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3. Outline dimensions - 240 Tape Ball Grid Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3. MAIN FUNCTIONS DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1. Programmable Demux ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2. Parallel output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3. Input clock sampling delay adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4. Asynchronous reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.5. ADC + DEMUX mono-channel applications : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.6. ADC + DEMUX multi-channel applications with asynchronous reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.7. Synchronous Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.8. ADC + DEMUX multi-channel applications with synchronous reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.9. 1:16 conversion ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.10. Counter programmable state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.11. Pipeline delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.12. 8 /10 bit, with nap mode for the 2 unused bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.13. ECL Differential input data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.14. 50 ohms Differential output data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.15. Single ended output data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.16. Differential Data Ready output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.17. Built-in Self Test (BIST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4. ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2/13
TS81102G0
1. BLOCK DIAGRAM
Data Path
DEMUXDelAdjCtrl
SwiAdj
VplusDOut
VCC
GND
VEE
DIODE
Clock Path
(to be confirmed)
SyncReset
AsyncReset
ADCDelAdjIn
ADCDelAdjCtrl
delay
ClkInType
RatioSel
FS/8
NAP
delay
B
2
BIST
8/10
mux
8/10
ClkPar
even
master
latch
even
slave
latch
odd
master
latch
odd
slave
latch
Phase
control
RstGen
Reset
mux
Counter
(8 stage
shift register)
8
ClkIn
8
Counter
Status
Latch Sel Even/Odd [1..8/10]
Port Selection Clock
8
FS/8
8
Data
Output
Clock
1
8/10
3
RatioSel
I[0..7/9]
NbBit
BIST
A[0..7/9]
RefA
C[0..7/9]
RefC
E[0..7/9]
RefE
G[0..7/9]
RefG
B[0..7/9]
RefB
D[0..7/9]
RefD
F[0..7/9]
RefF
H[0..7/9]
RefH
DataReady
generation
Even Ports
Odd Ports
DR/DR
3/13
ADCDelAdjOut
TS81102G0
2. PACKAGE DESCRIPTION
2.1. Pin description
Type
Digital Inputs
Name
I[0..9]
ClkIn
Outputs
A[0..9]
!
H[0..9]
Levels
Differential ECL
Differential ECL
Adjustable Logic
Single
Adjustable Logic
Differential
Adjustable Single
Comments
Data input.
on–chip 100 ohms differential adaptation resistor
Clock Input (Data Ready ADC).
on–chip 100 ohms differential adaptation resistor
Data output for port A to H.
Common mode is adjusted with VPlusDOut. Swing
is adjusted with SwiAdj. 50
W
adaptation possible.
Data ready for channel A to H.
Common mode is adjusted with VPlusDOut. Swing
is adjusted with SwiAdj. 50
W
adaptation possible.
Reference voltage for output channels A to H.
Common mode is adjusted with VPlusDOut.
50
W
adaptation possible.
DataReady or DataReady/2 :
logic 1 : Data Ready
DEMUX ratio ;
logic 1 : 1:4
Reset and Switch of Built–In Self Test (BIST) :
logic 0 : BIST active
Swing adjustement of output buffers :
SwiAdj = –0.5V : swing # 0.1 V
SwiAdj = 0.0V : swing = 0.5 V
SwiAdj = +0.5V : swing = 1.0 V
Diode for chip temperature measurement.
Number of bit 8 or 10 :
logic 1 : 10 bit
Asynchronous reset :
logic 1 : reset on
Synchronous reset :
on rising edge
(to be confirmed)
Control of the delay line of DataReady input :
differential input = –0.5 V : delay = 250 ps
differential input = 0.0 V : delay = 500 ps
differential input = 0.5 V : delay = 750 ps
Control of the delay line for ADC :
differential input = –0.5 V : delay = 250 ps
differential input = 0.0 V : delay = 500 ps
differential input = 0.5 V : delay = 750 ps
Stand–alone delay adjust input for ADC.Differential
adaptation of 100
W
inside the buffer.
Stand–alone delay adjust output for ADC
Common ground
Digital negative power supply
Common mode adjustement of output buffers
Digital positive power supply
DR
RefA
!
RefH
Control Signals
ClkInType
RatioSel
Bist
SwiAdj
TTL
TTL
TTL
0V
"
0.5 V
Diode
NbBit
Synchronization
AsyncReset
SyncReset
Analog
TTL
TTL
Differential ECL
DEMUXDelAdjCtrl
Differential analog
input of
"0.5
V
around 0.5 V com-
mon mode.
Differential analog
input of
"0.5
V
around 0.5 V com-
mon mode.
Differential ECL
50
W
differential
output
Ground 0V
Power –5V
Adjustable power
from 0V to +3.3V
Power +5V
ADCDelAdjCtrl
ADCDelAdjIn
ADCDelAdjOut
Power Supplies
GND
VEE
VplusDOut
VCC
4/13
TS81102G0
2.2. TBGA 240 package – Pinout
ro
w
col
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
1
2
3
name
NC
E3
E5
E7
E9
C0
C2
C4
C6
C8
REFA
A1
A3
A5
A7
A9
DEMUXDELADJCTRL
RSTSYNCB
NC
E1
E2
E4
E6
E8
REFC
C1
C3
C5
C7
C9
A0
A2
A4
A6
A8
ASYNCRESET
DEMUXDELADJCTRLB
RSTSYNC
REFE
E0
VEE
VPLUSDOUT
VPLUSDOUT
VPLUSDOUT
VPLUSDOUT
VEE
VPLUSDOUT
VEE
VPLUSDOUT
VEE
VPLUSDOUT
VPLUSDOUT
VPLUSDOUT
GND
GND
GND
DIODE
G8
G9
VEE
ro
w
col
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
1
2
3
4
16
17
18
19
1
2
3
4
16
17
18
19
1
2
3
4
16
17
18
19
1
2
3
4
16
17
18
19
1
2
3
4
16
17
18
19
1
2
3
4
name
VEE
VEE
VPLUSDOUT
VPLUSDOUT
VEE
VPLUSDOUT
VEE
VPLUSDOUT
VEE
VPLUSDOUT
GND
VCC
VCC
GND
I0B
I0
G6
G7
VPLUSDOUT
VEE
VEE
VEE
I1B
I1
G4
G5
GND
GND
GND
GND
I2B
I2
G2
G3
VEE
VEE
VEE
VEE
I3B
I3
G0
G1
GND
GND
GND
GND
CLKINB
CLKIN
DR
REFG
VPLUSDOUT
VCC
VEE
VEE
I4B
I4
SWIADJ
DRB
VEE
VEE
ro
w
col
16
17
18
19
1
2
3
4
16
17
18
19
1
2
3
4
16
17
18
19
1
2
3
4
16
17
18
19
1
2
3
4
16
17
18
19
1
2
3
4
16
17
18
19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
name
VEE
GND
I5B
I5
H9
RATIOSEL
VPLUSDOUT
VPLUSDOUT
VEE
VEE
I6B
I6
H7
H8
GND
GND
GND
GND
I7B
I7
H5
H6
VPLUSDOUT
VPLUSDOUT
VEE
VEE
I8B
I8
H3
H4
GND
GND
GND
GND
I9B
I9
H1
H2
VPLUSDOUT
VPLUSDOUT
VEE
GND
ADCDELADJOUT
ADCDELADJOUTB
REFH
H0
VEE
VEE
VEE
VPLUSDOUT
VPLUSDOUT
VEE
VPLUSDOUT
VEE
VPLUSDOUT
VEE
VPLUSDOUT
VPLUSDOUT
GND
VEE
ro
w
col
17
18
19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
name
VEE
ADCDELADJIN
ADCDELADJINB
F8
F9
VEE
VPLUSDOUT
VPLUSDOUT
VPLUSDOUT
VPLUSDOUT
VEE
VPLUSDOUT
VEE
VPLUSDOUT
VEE
VPLUSDOUT
VPLUSDOUT
VPLUSDOUT
GND
GND
GND
GND
F7
F6
F4
F2
F0
D9
D7
D5
D3
D1
REFD
B8
B6
B4
B2
B0
BIST
CLKINTYPE
ADCDELADJCTRL
NC
F5
F3
F1
REFF
D8
D6
D4
D2
D0
B9
B7
B5
B3
B1
REFB
NBBIT
ADCDELADJCTRLB
NC
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
E
E
E
E
E
E
E
E
F
F
F
F
F
F
F
F
G
G
G
G
G
G
G
G
H
H
H
H
H
H
H
H
J
J
J
J
J
J
J
J
K
K
K
K
K
K
K
K
L
L
L
L
L
L
L
L
M
M
M
M
M
M
M
M
N
N
N
N
N
N
N
N
P
P
P
P
P
P
P
P
R
R
R
R
R
R
R
R
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
5/13
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